{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "vref-dvth", "name": "Threshold-difference voltage reference", "group": "Mirrors, bias and references", "subgroup": "Voltage references", "title": "Threshold-difference voltage reference", "summary": "Generates about 0.35 V using a tiny leakage current. Two NMOS types with different thresholds balance opposing temperature effects; a third transistor shields the leakage source. Power is very low, but the output is weakly driven and its absolute voltage varies with process.", "reference": { "kind": "paper", "authors": "M. Seok, G. Kim, D. Blaauw, D. Sylvester", "title": "A portable 2-transistor picowatt temperature-compensated voltage reference operating at 0.5 V", "year": 2012, "where": "IEEE Journal of Solid-State Circuits, 47(10):2534-2545", "doi": "10.1109/JSSC.2012.2206683", "takes": "The topology: a transistor at V_GS = 0 whose leakage is the only bias, feeding a diode-connected thick-oxide transistor, their threshold difference falling with temperature against a logarithm of their size ratio rising with it. The paper's top device is a native NMOS; SG13G2 has none, so a 1.2 V core NMOS takes its place. The 3.3 V drain shield that keeps its thin oxide from tunnelling, the copy count that cancels the temperature coefficient and the sizing are this library's.", "also": [ { "authors": "E. Vittoz, J. Fellrath", "title": "CMOS analog integrated circuits based on weak inversion operations", "year": 1977, "where": "IEEE Journal of Solid-State Circuits, 12(3):224-231 - the weak-inversion law both transistors follow" } ] }, "resources": { "record": "/circuits/vref-dvth.json", "page": "/index.html#vref-dvth", "achieved": "/achieved/vref-dvth.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hv_tt.spice", "url": "/sg13g2_hv_tt.spice", "sha256": "e9b858ad4f7bba550467f1eddb6ca496bcc5f4644474f41240d63927934928ad" }, { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hv_tt.spice", "sg13g2_lv_tt.spice" ], "ports": [ { "name": "out", "kind": "output", "note": "V_ref: M2's gate and drain" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "MS", "type": "nmos", "nodes": "vdd vdd x vss", "sizedBy": [ "WS", "LS" ], "role": "3.3 V; the drain shield, diode-connected: holds M1's drain about 0.55 V below the supply", "fingers": 1, "copies": 1 }, { "name": "M1", "type": "nmos", "nodes": "x out out vss", "sizedBy": [ "W1", "L1", "N1" ], "role": "1.2 V; N1 copies of the unit at V_GS = 0: its leakage is the cell's current", "fingers": 1, "copies": 9 }, { "name": "M2", "type": "nmos", "nodes": "out out vss vss", "sizedBy": [ "W2", "L2" ], "role": "3.3 V; diode-connected: its V_GS is V_ref", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "threshold-difference", "of": [ "M1", "M2" ], "constraint": "V_ref ≈ (V_T0,M2 - V_T0,M1)/n + U_T ln(S_M1 I_0,M1/(S_M2 I_0,M2))", "why": "Both carry one current in weak inversion. M1's gate is on its source, which sits at V_ref, so it runs at V_GS = 0 with its source V_ref above its bulk; M2 at V_GS = V_ref. Equating the two currents leaves the thresholds' difference over n, about 0.3 V here, plus a logarithm of their sizes and specific currents. The current itself drops out, which is why a leakage current can bias a reference." }, { "rule": "zero-tc", "of": [ "M1" ], "constraint": "N1 copies: the rising term against the falling one", "why": "The 3.3 V threshold falls faster with temperature than the 1.2 V one, so their difference falls; U_T ln(size ratio) rises. Near the default count, adding a copy of the 1.2 V unit shifts the output by a few millivolts and changes its temperature slope. The dependence is logarithmic, not a constant step per copy. At the typical corner eight copies are flattest; nine centre the process draws, whose low-output tail leans the other way - 29 ppm/°C typical, at most 110 in any of 40 draws. Copies of one unit, not a wider device, because width moves the threshold (narrow-width effect) as well as the size; the count is also the natural trim, copies switched in or out per chip." }, { "rule": "shield", "of": [ "MS", "M1" ], "constraint": "M1's drain ≈ V_DD - V_GS,MS; V_DS,M1 ≈ 0.31 V", "why": "M1's gate is its source, V_ref, so without the shield the whole of V_DD - V_ref sat across its thin gate oxide at the drain edge, and electrons tunnelled through it into the picoamp node: in process draws where M1 leaked several times less than typical that bowed V_ref up by 20 to 25 mV at -40 °C and took the coefficient to 520 ppm/°C, and no copy count removes a bow. MS, a diode-connected 3.3 V NMOS - thick oxide, negligible gate tunnelling at these voltages - holds M1's drain 0.55 V below the supply, and the tunnelling falls by more than tenfold. M1 stays saturated: 0.31 V is well above the 4 U_T weak inversion needs." }, { "rule": "leakage-bias", "of": [ "M1" ], "constraint": "V_GS = 0; I ≈ 0.3 nA at 27 °C", "why": "No bias circuit: M1's subthreshold current at V_GS = 0 is the whole supply current - 4 pA at -40 °C to 15 nA at 125 °C, a factor of four thousand that V_ref does not see. It also sets the start-up: the node charges from that current alone, in 35 µs at 27 °C and 1.8 ms at -40 °C." }, { "rule": "thick-oxide", "of": [ "M2", "MS" ], "constraint": "3.3 V devices at a 1.2 V supply", "why": "M2 is a 3.3 V NMOS for its threshold, about 0.3 V above the 1.2 V device's, and MS for its thick oxide; nothing in the cell sees more than 1.32 V. M2's thick oxide also keeps its gate from leaking into the node it sits on." }, { "rule": "line", "of": [ "M1", "MS" ], "constraint": "L1 long: small barrier lowering", "why": "M1's drain follows the supply through the shield, so the supply reaches V_ref through M1's drain-induced barrier lowering, steeper at the shield's 0.31 V than at the full supply: 2 µm keeps it to 6.7 %/V, 5.6 mV over 1.08 to 1.32 V." } ], "specs": [ { "key": "vout_27", "label": "Output at 27 °C", "unit": "V", "direction": "target", "constraint": ">= 0.25 V, <= 0.43 V", "min": 0.25, "max": 0.43, "why": "The threshold difference over n plus U_T ln of the size ratio: 345 mV here, 332 to 352 mV over the corners. The 1.2 V and 3.3 V thresholds come from separate implants and move apart in each process draw: 274 to 399 mV over 40 Monte Carlo draws, which set this window. Mismatch alone moves it by about 4 mV and a copy of M1 by 3.5 mV, so neither sizing nor the copy trim closes that spread." }, { "key": "tc_ppm", "label": "Temperature coefficient, -40 to 125 °C", "unit": "ppm/°C", "direction": "min", "constraint": "<= 150 ppm/°C", "min": null, "max": 150, "why": "Nine copies of M1 put the rising term against the falling one: 29 ppm/°C from -40 to 125 °C. With M1's gate tunnelling taken off by the shield, what the process leaves is a slope: 9 to 123 ppm/°C over the corners and at most 110 ppm/°C in 40 Monte Carlo draws (520 before the shield); a copy or two of M1 more or less trims it." }, { "key": "line_pct", "label": "Line regulation", "unit": "%/V", "direction": "min", "constraint": "<= 10 %/V", "min": null, "max": 10, "why": "M1's drain follows the supply through the shield, and at 0.31 V of drain voltage its barrier lowering passes the change on to its current and so to V_ref: 5.6 mV over 1.08 to 1.32 V, 6.7 %/V (4.7 %/V unshielded)." }, { "key": "i_supply", "label": "Supply current at 27 °C", "unit": "A", "direction": "min", "constraint": "<= 4e-9 A", "min": null, "max": 4e-9, "why": "Nothing biases the cell but M1's leakage at V_GS = 0: 0.28 nA at 27 °C, 4 pA at -40 °C, 15 nA at 125 °C. A threshold 60 mV low multiplies it tenfold: up to 2.05 nA over 40 Monte Carlo draws, which set this limit." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 20 dB", "min": 20, "max": null, "why": "V_ref is a node of gigaohms: above a few hertz the ripple reaches it through the capacitances of M1 and the shield, divided against the capacitance of M2's gate: 32.6 dB at 1 kHz." }, { "key": "t_start", "label": "Start-up time, to 1 %", "unit": "s", "direction": "min", "constraint": "<= 0.002 s", "min": null, "max": 0.002, "why": "At power-up the node charges from M1's leakage alone: 35 µs at 27 °C and up to 0.23 ms over 40 draws there, 1.8 ms at -40 °C, where that leakage is a few picoamps." } ], "explanation": { "idea": "Generates about 0.35 V using a tiny leakage current. Two NMOS types with different thresholds balance opposing temperature effects; a third transistor shields the leakage source. Power is very low, but the output is weakly driven and its absolute voltage varies with process.", "detail": "A voltage reference from two transistors of different threshold and about 0.28 nA at the nominal condition. M1, nine copies of a 1.2 V NMOS unit with the gate on the source, passes only its subthreshold current; M2, a diode-connected 3.3 V NMOS whose threshold is about 0.3 V higher, must carry the same current, which fixes its V_GS, the output. In weak inversion that V_GS is the threshold difference over n plus U_T times a logarithm of the size ratio: the first falls with temperature, the second rises, and the copy count sets them to cancel. MS, a 3.3 V diode above M1, keeps the supply off M1's thin gate oxide, whose tunnelling would otherwise feed the picoamp node at the cold end.", "lesson": { "relation": 0, "symbols": "V_ref is output voltage; V_T0,M1 and V_T0,M2 are threshold parameters; n is the assumed common subthreshold slope factor; U_T = kT/q; S is effective device W/L including copies; I_0 is each device type's current prefactor.", "assumptions": "A simplified weak-inversion model with a common slope factor, M1 source-body effect included, and both devices saturated. Different device types, drain effects and leakage make this a design guide, not an exact law.", "exercise": { "param": "N1", "value": 10, "analysis": "temp", "expect": "Adding one leakage-source unit should raise the reference voltage and change its temperature slope. The shift per added unit is not constant because the size term is logarithmic." }, "limits": "The high-impedance output needs a nearly leakage-free load or suitable buffer. Absolute voltage varies substantially with process, and cold start-up is much slower than nominal." }, "path": [ { "part": "Drain shield", "devices": "MS", "does": "A diode-connected 3.3 V NMOS, 2 by 1 µm, from the supply to M1's drain: it holds that drain 0.55 V below the supply, so M1's gate oxide sees 0.31 V instead of 0.85 V and has much less gate tunnelling into V_ref; the shield's thick-oxide gate leakage is negligible at these voltages." }, { "part": "Leakage source", "devices": "M1", "does": "N1 = 9 copies of a 1 by 2 µm 1.2 V unit, gate and source on V_ref: at V_GS = 0 its subthreshold current is the cell's only bias, 0.28 nA at 27 °C." }, { "part": "Reference diode", "devices": "M2", "does": "A 3 by 2 µm 3.3 V NMOS, gate and drain on V_ref: it settles at the V_GS that carries M1's current, and that V_GS is the output, 345 mV." } ], "bias": "Nothing sets the current but M1's leakage at V_GS = 0, from 4 pA at −40 °C to 15 nA at 125 °C; the simplified weak-inversion law sets V_ref from thresholds and size ratio. Real drain and leakage effects still perturb it. The node is so weakly driven that it charges in 35 µs at 27 °C and 1.8 ms at −40 °C.", "relations": [ { "what": "Reference voltage", "expr": "V_ref ≈ (V_T0,M2 − V_T0,M1)/n + U_T ln(S_M1 I_0,M1 / (S_M2 I_0,M2))", "note": "simplified weak inversion with a common slope factor; M1's raised source introduces body effect" }, { "what": "Temperature coefficient", "expr": "dV_ref/dT ≈ d(V_T0,M2 − V_T0,M1)/dT / n + (k/q) ln(S_M1 I_0,M1 / (S_M2 I_0,M2))", "note": "the 3.3 V threshold falls faster; N1 = 9 balances the two: 29 ppm/°C from −40 to 125 °C, at most 110 ppm/°C over 40 Monte Carlo draws" }, { "what": "Process spread", "expr": "σ(V_ref) ≈ σ(V_T0,M2 − V_T0,M1)/n", "note": "the two thresholds come from separate implants and move apart from die to die: σ 30 to 35 mV over the draws, which a copy of M1, 3.5 mV, does not close" }, { "what": "Cell current", "expr": "I ≈ N1 I_0,M1 exp(−V_T,M1(V_ref)/(n U_T))", "note": "M1's leakage, V_T,M1 raised by the body effect at V_SB = V_ref" }, { "what": "Supply", "expr": "ΔV_ref ≈ σ_M1 ΔV_DD / n", "note": "M1's drain-induced barrier lowering, steeper at the shield's 0.31 V: 5.6 mV over 1.08 to 1.32 V, 6.7 %/V" } ], "tradeoffs": [ "N1 (copies of M1's unit): near the default, an added copy shifts the output by a few millivolts and changes its slope; the steps are logarithmic, not constant: the trim, since the 1.2 V and 3.3 V thresholds move apart over process and the slow and fast corners need a copy more or less.", "W2 and L2 (M2): the same balance from the other side - a larger M2 lowers V_ref and its slope with the current nearly unchanged.", "WS and LS (the shield): a smaller shield holds M1's drain lower, cutting its tunnelling further but steepening the barrier lowering that passes the supply to V_ref; without it, draws that leaked several times less than typical bowed up by 20 to 25 mV at −40 °C.", "L1 (M1's unit): longer cuts the barrier lowering, at the cost of M1's leakage and so of the start-up time." ] }, "sizing": [ { "key": "W1", "label": "W 1.2 V unit (M1)", "unit": "m", "value": 0.000001, "min": 3e-7, "max": 0.00001, "kind": "si" }, { "key": "L1", "label": "L 1.2 V unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.00001, "kind": "si" }, { "key": "N1", "label": "M1, copies of the unit", "unit": "", "value": 9, "min": 1, "max": 20, "kind": "int" }, { "key": "W2", "label": "W 3.3 V diode (M2)", "unit": "m", "value": 0.000003, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "L2", "label": "L 3.3 V diode", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.00001, "kind": "si" }, { "key": "WS", "label": "W 3.3 V drain shield (MS)", "unit": "m", "value": 0.000002, "min": 3e-7, "max": 0.00004, "kind": "si" }, { "key": "LS", "label": "L 3.3 V drain shield", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.00001, "kind": "si" } ], "testbenches": [ { "id": "temp", "label": "Against temperature", "note": "The output from -40 to 125 °C at the typical supply: its level, and how much it moves - the temperature coefficient, by the box method.", "measures": [], "metricKeys": [ "vout_27", "tc_ppm", "spread", "i_supply" ], "acceptance": [ "vout_27", "tc_ppm", "i_supply" ], "acceptanceRules": [ { "key": "vout_27", "unit": "V", "min": 0.25, "max": 0.43, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "tc_ppm", "unit": "ppm/°C", "min": null, "max": 150, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_supply", "unit": "A", "min": null, "max": 4e-9, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Threshold-difference voltage reference - the output against temperature\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt vrefdvt out vdd vss\n* MS: a 3.3 V diode from the supply, the drain shield: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=2u l=1u ng=1 m=1\n* M1: N1 copies of a 1.2 V unit at V_GS = 0, its subthreshold current the only bias\nXM1 x out out vss sg13_lv_nmos w=1u l=2u ng=1 m=9\n* M2: a 3.3 V diode, higher threshold, settling at the V_GS that carries it\nXM2 out out vss vss sg13_hv_nmos w=3u l=2u ng=1 m=1\n.ends\nXdut out vdd 0 vrefdvt\n.dc temp -40 125 5\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vout27 FIND v(out) AT=27\n.end" }, { "id": "line", "label": "Against the supply", "note": "The output over 1.08–1.32 V: line regulation uses the magnitude of its normalized endpoint change. The signed voltage change is retained separately.", "measures": [], "metricKeys": [ "line_mv", "line_pct" ], "acceptance": [ "line_pct" ], "acceptanceRules": [ { "key": "line_pct", "unit": "%/V", "min": null, "max": 10, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Threshold-difference voltage reference - the output against the supply\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt vrefdvt out vdd vss\n* MS: a 3.3 V diode from the supply, the drain shield: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=2u l=1u ng=1 m=1\n* M1: N1 copies of a 1.2 V unit at V_GS = 0, its subthreshold current the only bias\nXM1 x out out vss sg13_lv_nmos w=1u l=2u ng=1 m=9\n* M2: a 3.3 V diode, higher threshold, settling at the V_GS that carries it\nXM2 out out vss vss sg13_hv_nmos w=3u l=2u ng=1 m=1\n.ends\nXdut out vdd 0 vrefdvt\n.dc Vdd 1.08 1.32 0.01\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vlo FIND v(out) AT=1.08\n.meas dc vhi FIND v(out) AT=1.32\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 20, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Threshold-difference voltage reference - supply rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\n.subckt vrefdvt out vdd vss\n* MS: a 3.3 V diode from the supply, the drain shield: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=2u l=1u ng=1 m=1\n* M1: N1 copies of a 1.2 V unit at V_GS = 0, its subthreshold current the only bias\nXM1 x out out vss sg13_lv_nmos w=1u l=2u ng=1 m=9\n* M2: a 3.3 V diode, higher threshold, settling at the V_GS that carries it\nXM2 out out vss vss sg13_hv_nmos w=3u l=2u ng=1 m=1\n.ends\nXdut out vdd 0 vrefdvt\n.ac dec 20 1 1g\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas ac vdb_1k FIND vdb(out) AT=1k\n.end" }, { "id": "startup", "label": "Power-up", "note": "The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.", "measures": [], "metricKeys": [ "t_start" ], "acceptance": [ "t_start" ], "acceptanceRules": [ { "key": "t_start", "unit": "s", "min": null, "max": 0.002, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Threshold-difference voltage reference - the supply ramping up from zero\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 pwl(0 0 10u {VDD})\n.subckt vrefdvt out vdd vss\n* MS: a 3.3 V diode from the supply, the drain shield: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=2u l=1u ng=1 m=1\n* M1: N1 copies of a 1.2 V unit at V_GS = 0, its subthreshold current the only bias\nXM1 x out out vss sg13_lv_nmos w=1u l=2u ng=1 m=9\n* M2: a 3.3 V diode, higher threshold, settling at the V_GS that carries it\nXM2 out out vss vss sg13_hv_nmos w=3u l=2u ng=1 m=1\n.ends\nXdut out vdd 0 vrefdvt\n.tran 2u 4m\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran vend FIND v(out) AT=4m\n.end" } ], "measurements": { "vout_27": { "label": "Output at 27 °C", "unit": "V", "spec": { "min": 0.25, "max": 0.43 } }, "tc_ppm": { "label": "Temperature coefficient, -40 to 125 °C", "unit": "ppm/°C", "spec": { "min": null, "max": 150 } }, "line_pct": { "label": "Line regulation", "unit": "%/V", "spec": { "min": null, "max": 10 } }, "i_supply": { "label": "Supply current at 27 °C", "unit": "A", "spec": { "min": null, "max": 4e-9 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 20, "max": null } }, "t_start": { "label": "Start-up time, to 1 %", "unit": "s", "spec": { "min": null, "max": 0.002 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "5be58433c7bff70f767e4dcdebab57fe64c76689400879ebd3cf62cd4bea5958" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/vref-dvth.js", "sha256": "bdf4d51f600b6ae89e66730fa5c46ef8c253fa25d8f634f9b418ab9ab173abdb" }, "simulationFingerprints": { "temp": "d96e01a1666ab27ef5c6b8d237691fb55ea402eca6e62315c4174f5cbb88af9e", "line": "2c2d2caa550ebad349e22472fafbed70e6e15ff90997fd4c6d7adee4bdcec4f5", "psrr": "d0880d202595133ef7ef06c0454b2d1cdc8110af3f1f9de86a2519b27b036c95", "startup": "bf841af2cfb3f2e7418361b66a8da088dd3aa7c7524d5c946ef73ce957371d74" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "7630ca9b0fd889bcd9c82d53c35dec7d259902e7489f3406a34a3e227a13db5a", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "vref-dvth", "parameters": { "W1": 0.000001, "L1": 0.000002, "N1": 9, "W2": 0.000003, "L2": 0.000002, "WS": 0.000002, "LS": 0.000001 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/vref-dvth/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "vrefdvt", "ports": [ { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMS vdd vdd x vss sg13_hv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "vdd" }, { "id": "s", "net": "x" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=2u ng=1 m=9", "source": "XM1 x out out vss sg13_lv_nmos w=1u l=2u ng=1 m=9", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "out" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=3u l=2u ng=1 m=1", "source": "XM2 out out vss vss sg13_hv_nmos w=3u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "XMS", "pin": "d" }, { "device": "XMS", "pin": "g" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMS", "pin": "s" }, { "device": "XM1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMS", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "vrefdvt", "parametersOrValue": "", "source": "Xdut out vdd 0 vrefdvt", "pins": [ { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/vrefdvt" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/vrefdvt", "name": "vrefdvt", "ports": [ { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMS vdd vdd x vss sg13_hv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "vdd" }, { "id": "s", "net": "x" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=2u ng=1 m=9", "source": "XM1 x out out vss sg13_lv_nmos w=1u l=2u ng=1 m=9", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "out" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=3u l=2u ng=1 m=1", "source": "XM2 out out vss vss sg13_hv_nmos w=3u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "XMS", "pin": "d" }, { "device": "XMS", "pin": "g" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMS", "pin": "s" }, { "device": "XM1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMS", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/vrefdvt" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "3.3 V; the drain shield", "devices": [ { "scope": "dut", "device": "XMS" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "1.2 V; N1 copies of the unit at V_GS = 0: its leakage is the cell's current", "devices": [ { "scope": "dut", "device": "XM1" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "3.3 V; diode-connected: its V_GS is V_ref", "devices": [ { "scope": "dut", "device": "XM2" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "x", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "out", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "vrefdvt", "parametersOrValue": "", "source": "Xdut out vdd 0 vrefdvt", "pins": [ { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/vrefdvt" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/vrefdvt", "name": "vrefdvt", "ports": [ { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMS vdd vdd x vss sg13_hv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "vdd" }, { "id": "s", "net": "x" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=2u ng=1 m=9", "source": "XM1 x out out vss sg13_lv_nmos w=1u l=2u ng=1 m=9", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "out" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=3u l=2u ng=1 m=1", "source": "XM2 out out vss vss sg13_hv_nmos w=3u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "XMS", "pin": "d" }, { "device": "XMS", "pin": "g" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMS", "pin": "s" }, { "device": "XM1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMS", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/vrefdvt" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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