{
  "$schema": "https://aisic.dev/schemas/digital-ip.schema.json",
  "schema": "aisic.digital-ip/1",
  "recordVersion": 1,
  "entryType": "upstream-ip",
  "id": "ip-cv32e40p",
  "name": "CORE-V CV32E40P",
  "summary": "An OpenHW 32-bit RISC-V processor with a four-stage pipeline and configurable floating-point and DSP extensions.",
  "technology": "Technology-independent RTL",
  "resources": { "record": "/digital/ip-cv32e40p/design.json", "schema": "/schemas/digital-ip.schema.json", "page": "/digital.html#ip-cv32e40p/learn" },
  "upstream": {
    "repository": "https://github.com/openhwfoundation/cv32e40p",
    "maintainer": "OpenHW Foundation and CORE-V contributors",
    "version": "cv32e40p_v1.8.3",
    "commit": "360d272898d81806be3377193870dbf83a3ea79f",
    "checkedOn": "2026-09-29",
    "selection": "Latest published GitHub release when checked. The release label is distinct from the core's RTL freeze/verification version. CV32E40X and CV32E40S are different cores, not interchangeable revisions of P.",
    "license": "Repository LICENSE: Solderpad Hardware License 0.51. Some RTL files, including cv32e40p_top.sv, specify Apache-2.0 WITH SHL-2.1. Check each file and dependency before redistribution; do not apply one blanket license.",
    "files": [
      { "path": "README.md", "label": "Overview and verification scope" },
      { "path": "rtl/cv32e40p_top.sv", "label": "Top-level RTL and parameters" },
      { "path": "rtl/cv32e40p_core.sv", "label": "Processor core RTL" },
      { "path": "cv32e40p_manifest.flist", "label": "Source and include manifest" },
      { "path": "cv32e40p_fpu_manifest.flist", "label": "Optional FPU source manifest" },
      { "path": "docs/source/pipeline.rst", "label": "Exact pipeline and writeback behavior" },
      { "path": "example_tb/README.md", "label": "Upstream example testbench" },
      { "path": "LICENSE", "label": "Repository license" }
    ]
  },
  "configuration": {
    "name": "RV32IMC baseline (proposed first browser target)",
    "top": "cv32e40p_top",
    "scope": "Begin with FPU, ZFINX, COREV_PULP and COREV_CLUSTER disabled. Use the flip-flop register-file implementation and an explicit clock-gate model. No AiSIC elaboration or cell mapping has been performed.",
    "parameters": { "FPU": 0, "ZFINX": 0, "COREV_PULP": 0, "COREV_CLUSTER": 0, "NUM_MHPMCOUNTERS": 1 }
  },
  "lesson": {
    "idea": "CV32E40P separates instruction fetch, decode, execution and writeback into four pipeline stages. Different instructions can occupy different stages at once, while dependencies and memory responses still impose stalls.",
    "steps": [
      "Instruction fetch obtains and aligns instructions from the instruction interface.",
      "Decode interprets the instruction and reads the register operands. Control logic handles dependencies and exceptional conditions.",
      "The execute stage performs arithmetic and memory-address generation. ALU, multiply and divide results write directly from EX to the register file; load results write from WB. Not every instruction uses WB for its result.",
      "The system supplies instruction/data-memory handshakes, reset, boot and trap addresses, interrupts and debug inputs. It must not assume that memory responds in one cycle."
    ],
    "tradeoffs": [
      "Four stages describe pipeline organization, not a guarantee of one completed instruction per clock. Dependencies, branches, division and memory latency matter.",
      "Floating point and CORE-V/PULP extensions change the supported software and hardware configuration. Keep the first teaching target small and record enabled features.",
      "The upstream example testbench is for experimentation; full verification lives in core-v-verif. A successful example program does not replace that verification.",
      "CV32E40P, CV32E40X and CV32E40S should have separate records and evidence if added. This entry is P only."
    ],
    "exercise": "Follow two dependent arithmetic instructions through the four stages, then insert a load before them. Explain which result can be forwarded and when memory latency requires a stall."
  },
  "diagram": {
    "kind": "conceptual-architecture",
    "scope": "Simplified baseline pipeline: arithmetic writes directly from EX; loads write from WB. Arrows group stage flow and data paths. Forwarding, redirects, CSR/debug/interrupt control and external memory are omitted. Not a complete RTL netlist.",
    "nodes": [
      { "id": "fetch", "label": "Fetch", "detail": "IF", "column": 0, "row": 0 },
      { "id": "decode", "label": "Decode", "detail": "ID", "column": 1, "row": 0 },
      { "id": "execute", "label": "Execute", "detail": "EX · ALU / MUL / DIV", "column": 2, "row": 0 },
      { "id": "writeback", "label": "Writeback", "detail": "WB · load results", "column": 3, "row": 0 },
      { "id": "registers", "label": "Register file", "detail": "Operands / results", "column": 1, "row": 1 },
      { "id": "lsu", "label": "Load / store", "detail": "External data interface", "column": 2, "row": 1 }
    ],
    "edges": [
      { "from": "fetch", "to": "decode", "label": "Instruction" },
      { "from": "decode", "to": "execute", "label": "Operands and control" },
      { "from": "execute", "to": "writeback", "label": "Load operation advances to WB; arithmetic writes directly from EX" },
      { "from": "registers", "to": "decode", "label": "Operand reads" },
      { "from": "writeback", "to": "registers", "label": "Load result writeback" },
      { "from": "execute", "to": "registers", "label": "ALU, multiply and divide result writeback" },
      { "from": "execute", "to": "lsu", "label": "Memory address, store data and control" },
      { "from": "lsu", "to": "writeback", "label": "Load response for WB" }
    ]
  },
  "verificationPlan": [
    "Lock the full source manifest, register-file choice, clock-gate model and disabled optional extensions; qualify SystemVerilog elaboration in the browser toolchain.",
    "Provide a bounded instruction/data-memory wrapper and program loader. Check reset, wait states, branches, multiply/divide, exceptions and interrupt entry/return with explicit assertions.",
    "Use the matching official core-v-verif revision and an independent ISA reference to check retirement behavior; keep example-test and verification-suite evidence separate.",
    "Qualify an IHP mapping with functional comparison before adding Liberty-based timing. Do not claim a maximum frequency or tapeout readiness from a browser waveform."
  ],
  "stages": [
    { "id": "rtl", "label": "RTL simulation", "status": "unavailable", "reason": "Source reference only. A browser-compatible RTL model, memory wrapper and program testbench are not yet integrated." },
    { "id": "synthesis", "label": "Synthesis", "status": "unavailable", "reason": "Multi-file SystemVerilog, include order, register-file selection and clock-gating support must be qualified first." },
    { "id": "timing", "label": "Cell timing", "status": "unavailable", "reason": "No AiSIC IHP mapping or qualified timing simulation is published for this core." }
  ],
  "qualification": { "status": "source-reference", "browserRunnable": false, "note": "Pinned upstream source links and an AiSIC teaching explanation only. No RTL bundle, simulation result, synthesized netlist, IHP area/delay or fabrication claim is provided." },
  "references": [
    { "label": "Official release v1.8.3", "url": "https://github.com/openhwfoundation/cv32e40p/releases/tag/cv32e40p_v1.8.3" },
    { "label": "Official CORE-V verification repository", "url": "https://github.com/openhwfoundation/core-v-verif" }
  ]
}