{
  "$schema": "https://aisic.dev/schemas/digital-ip.schema.json",
  "schema": "aisic.digital-ip/1",
  "recordVersion": 1,
  "entryType": "upstream-ip",
  "id": "ip-ibex",
  "name": "Ibex RISC-V",
  "summary": "Run the pinned Ibex small RTL in your browser: inspect instruction retirement, memory waits and program checks.",
  "technology": "Technology-independent RTL",
  "resources": { "record": "/digital/ip-ibex/design.json", "schema": "/schemas/digital-ip.schema.json", "page": "/digital.html#ip-ibex/learn" },
  "runtime": {
    "engine": "ibex-small-verilator-wasm/1",
    "module": "/digital/ip-ibex/engine/ibex.js",
    "wasm": "/digital/ip-ibex/engine/ibex.wasm",
    "manifest": "/digital/ip-ibex/engine/manifest.json",
    "programs": "/digital/ip-ibex/programs.js",
    "modelSha256": "29799d3672f83978f028a50e3e7b0b75e8a454d9016f48662fc677e02d46f867"
  },
  "upstream": {
    "repository": "https://github.com/lowRISC/ibex",
    "maintainer": "lowRISC and Ibex contributors",
    "version": "master snapshot · 8150e6455b91",
    "commit": "8150e6455b91a7727960572bc90ab933286e6c3c",
    "checkedOn": "2026-09-29",
    "selection": "No GitHub release is published. Pin the current master commit, not an old PULPissimo integration tag. A snapshot is not a stable-release claim.",
    "license": "Apache-2.0 unless a file states otherwise; retain LICENSE, NOTICE and individual third-party notices when redistributing.",
    "files": [
      { "path": "README.md", "label": "Overview and configuration evidence" },
      { "path": "ibex_configs.yaml", "label": "Exact upstream configuration presets" },
      { "path": "ibex_core.core", "label": "Core source and dependency manifest" },
      { "path": "rtl/ibex_core.sv", "label": "Processor core RTL" },
      { "path": "rtl/ibex_if_stage.sv", "label": "Instruction fetch" },
      { "path": "rtl/ibex_id_stage.sv", "label": "Decode and execute control" },
      { "path": "examples/simple_system/README.md", "label": "Upstream system and memory example" },
      { "path": "LICENSE", "label": "License" },
      { "path": "NOTICE", "label": "Attribution notices" }
    ]
  },
  "configuration": {
    "name": "small · compiled RTL browser model",
    "top": "ibex_core",
    "scope": "The pinned small preset is compiled with Verilator and Emscripten: two pipeline stages, FF register file, RV32I integer operations, RV32MFast multiply/divide, RV32Zca compressed instructions, no cache, PMP or SecureIbex. ResetAll=1 is explicitly enabled for this deterministic teaching model. The bounded memory wrapper provides 64 KiB RAM, reset and a program at 0x80; responses take 1 plus the selected extra wait cycles. Two-state functional cycles are not physical timing. The full elaboration configuration and source hashes are in the build manifest.",
    "parameters": { "upstreamPreset": "small", "BaseIsa": "ibex_pkg::BaseIsaRV32I", "RV32M": "ibex_pkg::RV32MFast", "RV32B": "ibex_pkg::RV32BNone", "RV32ZC": "ibex_pkg::RV32Zca", "WritebackStage": 0, "ICache": 0, "SecureIbex": 0, "ResetAll": 1, "RegFile": "ibex_pkg::RegFileFF" }
  },
  "lesson": {
    "idea": "A processor turns a stream of instructions into register updates and memory transactions. The instruction set describes what software observes; the pipeline describes how this implementation does the work.",
    "steps": [
      "Fetch requests instruction bytes from external instruction memory. Compressed instructions are expanded before decoding.",
      "Decode reads operands and selects the ALU, multiply/divide unit or load/store operation. In the small preset, decode and execution share the second pipeline stage.",
      "Register results are written back; loads wait for a memory response. Branches and traps redirect instruction fetch, so not every cycle completes an instruction.",
      "A system wrapper must supply reset, boot configuration, instruction/data memory and interrupt/debug connections. The processor core alone is not a complete microcontroller."
    ],
    "tradeoffs": [
      "Start with the small preset before adding caches, a third pipeline stage or security features. Each configuration needs its own verification evidence.",
      "The upstream core has an extensive verification flow. AiSIC's three directed programs check selected retirements and final state, not that full flow, all instructions or every configuration. No IHP qualification is claimed.",
      "Run changes the program test and memory latency without synthesis. The actual pinned RTL is precompiled to WebAssembly, not replaced by an instruction-set emulator. Editing RTL needs a new model build; a general browser SystemVerilog compiler is not provided."
    ],
    "exercise": "Trace a load, an addition using its result, and a taken branch. Identify where memory latency stalls execution and which fetched instruction is discarded."
  },
  "diagram": {
    "kind": "conceptual-architecture",
    "scope": "Small-preset teaching view. Arrows group instruction, operand and memory transactions; they are not a complete RTL netlist. The fetch/decode link includes branch and trap redirection. External memories belong to the system wrapper.",
    "nodes": [
      { "id": "fetch", "label": "Fetch", "detail": "Pipeline stage 1", "column": 0, "row": 0 },
      { "id": "execute", "label": "Decode / execute", "detail": "Pipeline stage 2", "column": 1, "row": 0 },
      { "id": "lsu", "label": "Load / store", "detail": "Memory transactions", "column": 2, "row": 0 },
      { "id": "data", "label": "Data memory", "detail": "External to core", "column": 3, "row": 0 },
      { "id": "instructions", "label": "Instruction memory", "detail": "External to core", "column": 0, "row": 1 },
      { "id": "registers", "label": "Register file", "detail": "Operands / writeback", "column": 1, "row": 1 }
    ],
    "edges": [
      { "from": "fetch", "to": "execute", "label": "Instructions forward; redirects back to fetch", "bidirectional": true },
      { "from": "execute", "to": "lsu", "label": "Memory operation and load result", "bidirectional": true },
      { "from": "lsu", "to": "data", "label": "Memory request and response", "bidirectional": true },
      { "from": "instructions", "to": "fetch", "label": "Instruction request and response", "bidirectional": true },
      { "from": "registers", "to": "execute", "label": "Operand reads and result writeback", "bidirectional": true }
    ]
  },
  "verificationPlan": [
    "Built: pinned small-preset RTL and vendored dependencies, explicit FF register file, source hashes, corresponding-source archive and reproducible model build.",
    "Directed checks: reset, taken/untaken branches, compressed NOPs, word and byte memory access, signed multiplication/division, illegal-instruction trap and return, with selectable memory wait states.",
    "Instruction retirement is compared with a separate limited reference for these programs. This does not reproduce upstream verification or establish complete ISA compliance, interrupt/debug/security correctness or coverage closure.",
    "Not integrated: arbitrary RTL editing/compilation, program uploads, full ISA reference suites, IHP synthesis, mapped timing and physical signoff. These remain separate qualification stages."
  ],
  "stages": [
    { "id": "rtl", "label": "RTL simulation", "status": "available", "reason": "Pinned Ibex small RTL compiled to WebAssembly. Select a program and memory wait states; inspect cycle signals, retirement and explicit checks. No synthesis needed." },
    { "id": "synthesis", "label": "Synthesis", "status": "unavailable", "reason": "The existing one-file Yosys flow does not yet resolve this processor's packages, configurations and dependencies." },
    { "id": "timing", "label": "Cell timing", "status": "unavailable", "reason": "No AiSIC IHP mapping or qualified timing simulation is published for this core." }
  ],
  "qualification": { "status": "directed-rtl-tests", "browserRunnable": true, "note": "Executable compiled RTL model with bounded directed program checks and independent retirement checking for their exercised instructions. Two-state cycle simulation, not full CPU verification, arbitrary-source browser compilation, IHP mapping, measured physical timing or fabrication evidence." },
  "references": [
    { "label": "Official lowRISC repository", "url": "https://github.com/lowRISC/ibex" },
    { "label": "Official Ibex manual (rolling documentation)", "url": "https://ibex-core.readthedocs.io/en/latest/" }
  ]
}