{ "schema": "aisic.digital-design/1", "id": "logic-counter4", "name": "4-bit synchronous counter", "domain": "digital", "technology": "IHP SG13G2 130 nm", "summary": "Four flip-flops and next-state logic count modulo 16, with enable and reset.", "lesson": { "idea": "All four state bits share one clock. Combinational logic computes the next count, and muxes hold the old state when EN is low.", "steps": [ "Compute bit toggles from the lower bits.", "Use enable muxes before four resettable flip-flops.", "Verify hold, increment, wraparound and asynchronous reset." ], "tradeoffs": [ "The carry chain affects the register-to-register path, so frequency needs timing analysis rather than a truth-table check.", "The shown cell areas exclude placement whitespace, clock tree, routing, taps, power delivery and pads." ], "exercise": "Find a held count and the 15-to-0 wraparound. Why is this a synchronous counter rather than a ripple counter?" }, "stages": [ { "id": "logic", "label": "Logic check", "status": "available", "reason": "Fast ideal zero-delay evaluation of the published explicit cell connections and testbench checks. No synthesis, RTL interpretation, transistor voltages, device corners or physical delay is modeled.", "artifacts": [ { "kind": "verilog", "label": "Structural cell example", "url": "/digital/logic-counter4/cells.v" }, { "kind": "json", "label": "Stimuli and assertions", "url": "/digital/logic-counter4/testbench.json" } ] }, { "id": "transistor", "label": "Cell transistors", "status": "available", "reason": "Live browser ngspice/WebAssembly transient simulation of IHP standard-cell transistors. The included example netlist is hand-written; a separate browser Yosys run generates the post-synthesis netlist. No routed parasitics, static timing closure, DRC/LVS or silicon proof.", "artifacts": [ { "kind": "verilog", "label": "Structural cell example", "url": "/digital/logic-counter4/cells.v" }, { "kind": "json", "label": "Stimuli and assertions", "url": "/digital/logic-counter4/testbench.json" } ], "corners": [ { "id": "typ", "label": "typ: 1.2 V, 25 \u00b0C" }, { "id": "slow", "label": "slow: 1.08 V, 125 \u00b0C" }, { "id": "fast", "label": "fast: 1.32 V, -40 \u00b0C" } ] }, { "id": "rtl", "label": "RTL", "status": "unavailable", "reason": "Synthesizable source is provided. No standalone browser RTL event simulator is bundled.", "artifacts": [ { "kind": "verilog", "label": "RTL source", "url": "/digital/logic-counter4/rtl.v" } ] }, { "id": "gate-delay", "label": "Gate delays", "status": "available", "reason": "Event-driven simulation of the synthesized cells with IHP Liberty delay-table interpolation, fanout capacitance and external output loads. Fixed slew at all cell inputs; maximum delay over arcs per output, not sensitized-path timing. No wire delays, setup/hold checks, SDF annotation or STA.", "artifacts": [ { "kind": "verilog", "label": "RTL source", "url": "/digital/logic-counter4/rtl.v" } ], "corners": [ { "id": "typ", "label": "typ: 1.2 V, 25 \u00b0C" }, { "id": "slow", "label": "slow: 1.08 V, 125 \u00b0C" }, { "id": "fast", "label": "fast: 1.32 V, -40 \u00b0C" } ] }, { "id": "timing", "label": "SPICE \u00b7 mapped cells", "status": "available", "reason": "After the separate browser Yosys synthesis action, ngspice simulates the mapped IHP cell transistors. Every simulation runs fresh; the mapping stays in this tab. Detailed runs may take tens of seconds. Not SDF simulation, STA or post-layout timing.", "artifacts": [ { "kind": "verilog", "label": "Synthesizable RTL", "url": "/digital/logic-counter4/rtl.v" } ], "corners": [ { "id": "typ", "label": "typ: 1.2 V, 25 \u00b0C" }, { "id": "slow", "label": "slow: 1.08 V, 125 \u00b0C" }, { "id": "fast", "label": "fast: 1.32 V, -40 \u00b0C" } ] } ], "cells": [ { "name": "sg13g2_and2_1", "count": 2 }, { "name": "sg13g2_dfrbpq_1", "count": 4 }, { "name": "sg13g2_inv_1", "count": 1 }, { "name": "sg13g2_mux2_1", "count": 4 }, { "name": "sg13g2_xor2_1", "count": 3 } ], "cellCount": 14, "cellAreaUm2": 335.664, "instances": [ { "type": "sg13g2_inv_1", "name": "u_toggle0", "connections": { "Y": "t0", "A": "Q[0]" } }, { "type": "sg13g2_xor2_1", "name": "u_toggle1", "connections": { "X": "t1", "A": "Q[1]", "B": "Q[0]" } }, { "type": "sg13g2_and2_1", "name": "u_carry2", "connections": { "X": "c2", "A": "Q[0]", "B": "Q[1]" } }, { "type": "sg13g2_xor2_1", "name": "u_toggle2", "connections": { "X": "t2", "A": "Q[2]", "B": "c2" } }, { "type": "sg13g2_and2_1", "name": "u_carry3", "connections": { "X": "c3", "A": "c2", "B": "Q[2]" } }, { "type": "sg13g2_xor2_1", "name": "u_toggle3", "connections": { "X": "t3", "A": "Q[3]", "B": "c3" } }, { "type": "sg13g2_mux2_1", "name": "u_enable0", "connections": { "X": "d0", "A0": "Q[0]", "A1": "t0", "S": "EN" } }, { "type": "sg13g2_mux2_1", "name": "u_enable1", "connections": { "X": "d1", "A0": "Q[1]", "A1": "t1", "S": "EN" } }, { "type": "sg13g2_mux2_1", "name": "u_enable2", "connections": { "X": "d2", "A0": "Q[2]", "A1": "t2", "S": "EN" } }, { "type": "sg13g2_mux2_1", "name": "u_enable3", "connections": { "X": "d3", "A0": "Q[3]", "A1": "t3", "S": "EN" } }, { "type": "sg13g2_dfrbpq_1", "name": "u_ff0", "connections": { "Q": "Q[0]", "CLK": "CLK", "D": "d0", "RESET_B": "RESET_B" } }, { "type": "sg13g2_dfrbpq_1", "name": "u_ff1", "connections": { "Q": "Q[1]", "CLK": "CLK", "D": "d1", "RESET_B": "RESET_B" } }, { "type": "sg13g2_dfrbpq_1", "name": "u_ff2", "connections": { "Q": "Q[2]", "CLK": "CLK", "D": "d2", "RESET_B": "RESET_B" } }, { "type": "sg13g2_dfrbpq_1", "name": "u_ff3", "connections": { "Q": "Q[3]", "CLK": "CLK", "D": "d3", "RESET_B": "RESET_B" } } ], "simulation": { "inputs": [ { "name": "CLK", "transitions": [ [ 0, 0 ], [ 12.5, 1 ], [ 17.5, 0 ], [ 22.5, 1 ], [ 27.5, 0 ], [ 32.5, 1 ], [ 37.5, 0 ], [ 42.5, 1 ], [ 47.5, 0 ], [ 52.5, 1 ], [ 57.5, 0 ], [ 62.5, 1 ], [ 67.5, 0 ], [ 72.5, 1 ], [ 77.5, 0 ], [ 82.5, 1 ], [ 87.5, 0 ], [ 92.5, 1 ], [ 97.5, 0 ], [ 102.5, 1 ], [ 107.5, 0 ], [ 112.5, 1 ], [ 117.5, 0 ], [ 122.5, 1 ], [ 127.5, 0 ], [ 132.5, 1 ], [ 137.5, 0 ], [ 142.5, 1 ], [ 147.5, 0 ], [ 152.5, 1 ], [ 157.5, 0 ], [ 162.5, 1 ], [ 167.5, 0 ], [ 172.5, 1 ], [ 177.5, 0 ], [ 182.5, 1 ], [ 187.5, 0 ], [ 192.5, 1 ], [ 197.5, 0 ], [ 202.5, 1 ], [ 207.5, 0 ] ] }, { "name": "RESET_B", "transitions": [ [ 0, 1 ], [ 1, 0 ], [ 10, 1 ], [ 211, 0 ] ] }, { "name": "EN", "transitions": [ [ 0, 0 ], [ 20, 1 ], [ 80, 0 ], [ 90, 1 ], [ 150, 0 ], [ 160, 1 ] ] } ], "output": "Q", "outputWidth": 4, "endTimeNs": 221, "transitionNs": 0.1, "outputLoadFf": 10, "maxStepNs": 0.02, "checks": [ { "timeNs": 3, "expected": "0000" }, { "timeNs": 14.5, "expected": "0000" }, { "timeNs": 24.5, "expected": "0001" }, { "timeNs": 34.5, "expected": "0010" }, { "timeNs": 44.5, "expected": "0011" }, { "timeNs": 54.5, "expected": "0100" }, { "timeNs": 64.5, "expected": "0101" }, { "timeNs": 74.5, "expected": "0110" }, { "timeNs": 84.5, "expected": "0110" }, { "timeNs": 94.5, "expected": "0111" }, { "timeNs": 104.5, "expected": "1000" }, { "timeNs": 114.5, "expected": "1001" }, { "timeNs": 124.5, "expected": "1010" }, { "timeNs": 134.5, "expected": "1011" }, { "timeNs": 144.5, "expected": "1100" }, { "timeNs": 154.5, "expected": "1100" }, { "timeNs": 164.5, "expected": "1101" }, { "timeNs": 174.5, "expected": "1110" }, { "timeNs": 184.5, "expected": "1111" }, { "timeNs": 194.5, "expected": "0000" }, { "timeNs": 204.5, "expected": "0001" }, { "timeNs": 213, "expected": "0000" } ] }, "top": "logic_counter4_rtl", "rtl": "// AiSIC synthesizable teaching RTL.\n`timescale 1ns/1ps\nmodule logic_counter4_rtl (input CLK, RESET_B, EN, output reg [3:0] Q);\n always @(posedge CLK or negedge RESET_B) if (!RESET_B) Q <= 4'b0000; else if (EN) Q <= Q + 4'b0001;\nendmodule\n", "cellNetlist": "// Hand-written IHP structural example; not a synthesis output.\nmodule logic_counter4_cells (input CLK, RESET_B, EN, output wire [3:0] Q);\nwire t0,t1,t2,t3,c2,c3,d0,d1,d2,d3;\n sg13g2_inv_1 u_toggle0 (.Y(t0), .A(Q[0]));\n sg13g2_xor2_1 u_toggle1 (.X(t1), .A(Q[1]), .B(Q[0]));\n sg13g2_and2_1 u_carry2 (.X(c2), .A(Q[0]), .B(Q[1]));\n sg13g2_xor2_1 u_toggle2 (.X(t2), .A(Q[2]), .B(c2));\n sg13g2_and2_1 u_carry3 (.X(c3), .A(c2), .B(Q[2]));\n sg13g2_xor2_1 u_toggle3 (.X(t3), .A(Q[3]), .B(c3));\n sg13g2_mux2_1 u_enable0 (.X(d0), .A0(Q[0]), .A1(t0), .S(EN));\n sg13g2_mux2_1 u_enable1 (.X(d1), .A0(Q[1]), .A1(t1), .S(EN));\n sg13g2_mux2_1 u_enable2 (.X(d2), .A0(Q[2]), .A1(t2), .S(EN));\n sg13g2_mux2_1 u_enable3 (.X(d3), .A0(Q[3]), .A1(t3), .S(EN));\n sg13g2_dfrbpq_1 u_ff0 (.Q(Q[0]), .CLK(CLK), .D(d0), .RESET_B(RESET_B));\n sg13g2_dfrbpq_1 u_ff1 (.Q(Q[1]), .CLK(CLK), .D(d1), .RESET_B(RESET_B));\n sg13g2_dfrbpq_1 u_ff2 (.Q(Q[2]), .CLK(CLK), .D(d2), .RESET_B(RESET_B));\n sg13g2_dfrbpq_1 u_ff3 (.Q(Q[3]), .CLK(CLK), .D(d3), .RESET_B(RESET_B));\nendmodule\n", "resources": { "record": "/digital/logic-counter4/design.json", "rtl": "/digital/logic-counter4/rtl.v", "testbench": "/digital/logic-counter4/testbench.json", "netlist": "/digital/logic-counter4/cells.v", "page": "/digital.html#logic-counter4", "schema": "/schemas/digital-design.schema.json", "urlBase": "Resource URLs start at this site's root." }, "evidence": { "pdkCommit": "68c1265b1c4e5e1b4613bef34b9ce7bfe4b2c957", "libraryFiles": { "typ": { "url": "/digital/library/sg13g2_stdcell_typ_1p20V_25C.lib", "sha256": "7677a8918689f452e80405ad16a83e744709342574f2aedcc507c2758986b396", "voltage": 1.2, "temperatureC": 25 }, "slow": { "url": "/digital/library/sg13g2_stdcell_slow_1p08V_125C.lib", "sha256": "1ac6a0301184b3a8aa1a4a01910967f624c8e869517777f529985f11f04588c3", "voltage": 1.08, "temperatureC": 125 }, "fast": { "url": "/digital/library/sg13g2_stdcell_fast_1p32V_m40C.lib", "sha256": "f191a3132d0f2f59ca2721884cdb1d8360c8fbf3e0012056af62583dd69ae701", "voltage": 1.32, "temperatureC": -40 } }, "sourceHashes": { "rtl.v": "68c92f49976de876c92c18ce55119eec58c9b7a0cd15f1caa8585c60dd4f3743", "cells.v": "b5a50fc91fcfb1fb58b3f834d610a908341c0aa92162456b8748bacb674a5990", "testbench.json": "0d5b7bead1c9e71a866f7d4e43f18b8f2205e36eadc2c118e7772d363cda5b4d" } }, "qualification": { "status": "demonstration-tests-only", "analogStudyIncluded": false, "delayLimits": "informational", "note": "Each browser run checks its finite truth-table or sequence. These new digital designs have not completed the 11-corner and 40-seed analog qualification protocol." }, "boundary": "Fast mode checks ideal zero-delay behavior of the published explicit cells; it is not RTL simulation or physical timing. Detailed modes simulate IHP cell transistors, directly or after browser Yosys synthesis. No routed parasitics, static timing closure, DRC/LVS or silicon proof.", "recordVersion": 1, "entryType": "library-block", "group": "Digital logic", "subgroup": "Sequential logic", "kind": "sequential", "reference": null, "implementation": { "kind": "standard-cell-reference", "evidence": "transistor-simulation", "purpose": "A small digital block for learning, reuse and retargeting; not a claim of optimal implementation.", "netlistBoundary": "The included structural example is hand-written. Browser synthesis generates a separate cell netlist, and simulation adds ideal stimuli, supply and loads.", "physicalSignoff": "No placed/routed layout, extracted interconnect, DRC/LVS or silicon measurements." }, "diagram": { "schema": "aisic.diagram/1", "kind": "cell-connectivity", "representation": "explicit-cell-example", "ports": [ { "id": "CLK", "name": "CLK", "direction": "input", "width": 1, "nets": [ "CLK" ] }, { "id": "RESET_B", "name": "RESET_B", "direction": "input", "width": 1, "nets": [ "RESET_B" ] }, { "id": "EN", "name": "EN", "direction": "input", "width": 1, "nets": [ "EN" ] }, { "id": "Q", "name": "Q", "direction": "output", "width": 4, "nets": [ "Q[0]", "Q[1]", "Q[2]", "Q[3]" ] } ], "nodes": [ { "id": "u_toggle0", "kind": "logic-cell", "cell": "sg13g2_inv_1", "family": "inv", "sequential": false, "ports": [ { "name": "Y", "direction": "output", "net": "t0" }, { "name": "A", "direction": "input", "net": "Q[0]" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_toggle1", "kind": "logic-cell", "cell": "sg13g2_xor2_1", "family": "xor2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "t1" }, { "name": "A", "direction": "input", "net": "Q[1]" }, { "name": "B", "direction": "input", "net": "Q[0]" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_carry2", "kind": "logic-cell", "cell": "sg13g2_and2_1", "family": "and2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "c2" }, { "name": "A", "direction": "input", "net": "Q[0]" }, { "name": "B", "direction": "input", "net": "Q[1]" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_toggle2", "kind": "logic-cell", "cell": "sg13g2_xor2_1", "family": "xor2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "t2" }, { "name": "A", "direction": "input", "net": "Q[2]" }, { "name": "B", "direction": "input", "net": "c2" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_carry3", "kind": "logic-cell", "cell": "sg13g2_and2_1", "family": "and2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "c3" }, { "name": "A", "direction": "input", "net": "c2" }, { "name": "B", "direction": "input", "net": "Q[2]" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_toggle3", "kind": "logic-cell", "cell": "sg13g2_xor2_1", "family": "xor2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "t3" }, { "name": "A", "direction": "input", "net": "Q[3]" }, { "name": "B", "direction": "input", "net": "c3" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_enable0", "kind": "logic-cell", "cell": "sg13g2_mux2_1", "family": "mux2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "d0" }, { "name": "A0", "direction": "input", "net": "Q[0]" }, { "name": "A1", "direction": "input", "net": "t0" }, { "name": "S", "direction": "input", "net": "EN" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_enable1", "kind": "logic-cell", "cell": "sg13g2_mux2_1", "family": "mux2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "d1" }, { "name": "A0", "direction": "input", "net": "Q[1]" }, { "name": "A1", "direction": "input", "net": "t1" }, { "name": "S", "direction": "input", "net": "EN" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_enable2", "kind": "logic-cell", "cell": "sg13g2_mux2_1", "family": "mux2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "d2" }, { "name": "A0", "direction": "input", "net": "Q[2]" }, { "name": "A1", "direction": "input", "net": "t2" }, { "name": "S", "direction": "input", "net": "EN" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_enable3", "kind": "logic-cell", "cell": "sg13g2_mux2_1", "family": "mux2", "sequential": false, "ports": [ { "name": "X", "direction": "output", "net": "d3" }, { "name": "A0", "direction": "input", "net": "Q[3]" }, { "name": "A1", "direction": "input", "net": "t3" }, { "name": "S", "direction": "input", "net": "EN" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_ff0", "kind": "logic-cell", "cell": "sg13g2_dfrbpq_1", "family": "dfrbpq", "sequential": true, "ports": [ { "name": "Q", "direction": "output", "net": "Q[0]" }, { "name": "CLK", "direction": "input", "net": "CLK" }, { "name": "D", "direction": "input", "net": "d0" }, { "name": "RESET_B", "direction": "input", "net": "RESET_B" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_ff1", "kind": "logic-cell", "cell": "sg13g2_dfrbpq_1", "family": "dfrbpq", "sequential": true, "ports": [ { "name": "Q", "direction": "output", "net": "Q[1]" }, { "name": "CLK", "direction": "input", "net": "CLK" }, { "name": "D", "direction": "input", "net": "d1" }, { "name": "RESET_B", "direction": "input", "net": "RESET_B" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_ff2", "kind": "logic-cell", "cell": "sg13g2_dfrbpq_1", "family": "dfrbpq", "sequential": true, "ports": [ { "name": "Q", "direction": "output", "net": "Q[2]" }, { "name": "CLK", "direction": "input", "net": "CLK" }, { "name": "D", "direction": "input", "net": "d2" }, { "name": "RESET_B", "direction": "input", "net": "RESET_B" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] }, { "id": "u_ff3", "kind": "logic-cell", "cell": "sg13g2_dfrbpq_1", "family": "dfrbpq", "sequential": true, "ports": [ { "name": "Q", "direction": "output", "net": "Q[3]" }, { "name": "CLK", "direction": "input", "net": "CLK" }, { "name": "D", "direction": "input", "net": "d3" }, { "name": "RESET_B", "direction": "input", "net": "RESET_B" } ], "powerPorts": [ { "name": "VDD", "net": "vdd" }, { "name": "VSS", "net": "0" } ] } ], "nets": [ { "id": "CLK", "endpoints": [ { "node": "$ports", "port": "CLK", "bit": 0, "role": "driver" }, { "node": "u_ff0", "port": "CLK", "role": "sink" }, { "node": "u_ff1", "port": "CLK", "role": "sink" }, { "node": "u_ff2", "port": "CLK", "role": "sink" }, { "node": "u_ff3", "port": "CLK", "role": "sink" } ] }, { "id": "RESET_B", "endpoints": [ { "node": "$ports", "port": "RESET_B", "bit": 0, "role": "driver" }, { "node": "u_ff0", "port": "RESET_B", "role": "sink" }, { "node": "u_ff1", "port": "RESET_B", "role": "sink" }, { "node": "u_ff2", "port": "RESET_B", "role": "sink" }, { "node": "u_ff3", "port": "RESET_B", "role": "sink" } ] }, { "id": "EN", "endpoints": [ { "node": "$ports", "port": "EN", "bit": 0, "role": "driver" }, { "node": "u_enable0", "port": "S", "role": "sink" }, { "node": "u_enable1", "port": "S", "role": "sink" }, { "node": "u_enable2", "port": "S", "role": "sink" }, { "node": "u_enable3", "port": "S", "role": "sink" } ] }, { "id": "Q[0]", "endpoints": [ { "node": "$ports", "port": "Q", "bit": 0, "role": "sink" }, { "node": "u_toggle0", "port": "A", "role": "sink" }, { "node": "u_toggle1", "port": "B", "role": "sink" }, { "node": "u_carry2", "port": "A", "role": "sink" }, { "node": "u_enable0", "port": "A0", "role": "sink" }, { "node": "u_ff0", "port": "Q", "role": "driver" } ] }, { "id": "Q[1]", "endpoints": [ { "node": "$ports", "port": "Q", "bit": 1, "role": "sink" }, { "node": "u_toggle1", "port": "A", "role": "sink" }, { "node": "u_carry2", "port": "B", "role": "sink" }, { "node": "u_enable1", "port": "A0", "role": "sink" }, { "node": "u_ff1", "port": "Q", "role": "driver" } ] }, { "id": "Q[2]", "endpoints": [ { "node": "$ports", "port": "Q", "bit": 2, "role": "sink" }, { "node": "u_toggle2", "port": "A", "role": "sink" }, { "node": "u_carry3", "port": "B", "role": "sink" }, { "node": "u_enable2", "port": "A0", "role": "sink" }, { "node": "u_ff2", "port": "Q", "role": "driver" } ] }, { "id": "Q[3]", "endpoints": [ { "node": "$ports", "port": "Q", "bit": 3, "role": "sink" }, { "node": "u_toggle3", "port": "A", "role": "sink" }, { "node": "u_enable3", "port": "A0", "role": "sink" }, { "node": "u_ff3", "port": "Q", "role": "driver" } ] }, { "id": "t0", "endpoints": [ { "node": "u_toggle0", "port": "Y", "role": "driver" }, { "node": "u_enable0", "port": "A1", "role": "sink" } ] }, { "id": "t1", "endpoints": [ { "node": "u_toggle1", "port": "X", "role": "driver" }, { "node": "u_enable1", "port": "A1", "role": "sink" } ] }, { "id": "c2", "endpoints": [ { "node": "u_carry2", "port": "X", "role": "driver" }, { "node": "u_toggle2", "port": "B", "role": "sink" }, { "node": "u_carry3", "port": "A", "role": "sink" } ] }, { "id": "t2", "endpoints": [ { "node": "u_toggle2", "port": "X", "role": "driver" }, { "node": "u_enable2", "port": "A1", "role": "sink" } ] }, { "id": "c3", "endpoints": [ { "node": "u_carry3", "port": "X", "role": "driver" }, { "node": "u_toggle3", "port": "B", "role": "sink" } ] }, { "id": "t3", "endpoints": [ { "node": "u_toggle3", "port": "X", "role": "driver" }, { "node": "u_enable3", "port": "A1", "role": "sink" } ] }, { "id": "d0", "endpoints": [ { "node": "u_enable0", "port": "X", "role": "driver" }, { "node": "u_ff0", "port": "D", "role": "sink" } ] }, { "id": "d1", "endpoints": [ { "node": "u_enable1", "port": "X", "role": "driver" }, { "node": "u_ff1", "port": "D", "role": "sink" } ] }, { "id": "d2", "endpoints": [ { "node": "u_enable2", "port": "X", "role": "driver" }, { "node": "u_ff2", "port": "D", "role": "sink" } ] }, { "id": "d3", "endpoints": [ { "node": "u_enable3", "port": "X", "role": "driver" }, { "node": "u_ff3", "port": "D", "role": "sink" } ] } ], "powerNets": [ { "id": "vdd", "role": "supply" }, { "id": "0", "role": "ground" } ], "scope": "Logical connectivity of the explicit cell example; power connections are listed separately. Not the synthesized result or a physical layout." }, "ports": [ { "id": "CLK", "name": "CLK", "direction": "input", "width": 1, "nets": [ "CLK" ] }, { "id": "RESET_B", "name": "RESET_B", "direction": "input", "width": 1, "nets": [ "RESET_B" ] }, { "id": "EN", "name": "EN", "direction": "input", "width": 1, "nets": [ "EN" ] }, { "id": "Q", "name": "Q", "direction": "output", "width": 4, "nets": [ "Q[0]", "Q[1]", "Q[2]", "Q[3]" ] } ], "authoring": { "schema": "aisic.authoring/1", "source": "/digital/logic-counter4/design.json", "canonicalFields": [ "name", "summary", "lesson", "boundary", "group", "subgroup", "reference", "implementation", "qualification" ], "explanationField": "lesson", "unknownFields": "preserved", "generatedFields": [ "schema", "recordVersion", "entryType", "id", "domain", "technology", "kind", "ports", "stages", "cells", "cellCount", "cellAreaUm2", "instances", "simulation", "top", "rtl", "cellNetlist", "resources", "evidence", "diagram", "authoring", "generated" ], "generatedStageFields": [ "id", "status", "artifacts", "corners" ], "generatedResourceFields": [ "record", "page", "rtl", "testbench", "netlist", "schema", "urlBase" ], "note": "Edit the lesson only here; it is the explanation used by people and AI. The data builder preserves authored fields and unknown extensions. Numerical recipes remain in tools/digital_flow.py." }, "generated": { "schema": "aisic.generated/1", "builder": "tools/digital_flow.py", "builderSha256": "3aa880c92a73d16c6e3e2787d6a6145aa2705f273c8664493eb627c67c127a6a", "authoredSha256": "ca3bb8d55aae24e318e637a3fff30ce84cd11ea0b596dd49e5aaa144f6bb8722", "diagramSha256": "e93eb59b8114a1639e41f8b897ae431694c556a46bee999d7b5d248d74cb5d44", "numericalSha256": "2de047890d07ade186e61a6c86a53907a4eb61d571a7117414a52ade97faacdb", "evidencePolicy": "This data build does not run simulations or certify existing evidence. Compare source fingerprints before reusing results." } }