{
  "schema": "aisic.digital-design/1",
  "id": "logic-inverter",
  "name": "Inverter",
  "domain": "digital",
  "technology": "IHP SG13G2 130 nm",
  "summary": "One input, the opposite output: the simplest standard-cell example.",
  "lesson": {
    "idea": "RTL states the Boolean function. The cell netlist chooses a physical library cell with a drive strength and a characterized delay.",
    "steps": [
      "Invert A in RTL.",
      "Connect one sg13g2_inv_1 cell.",
      "Use Logic check for the ideal function, then Cell transistors to inspect finite propagation delay."
    ],
    "tradeoffs": [
      "A larger drive cell usually trades more area and input capacitance for stronger output drive.",
      "Delay depends on process, supply, temperature, input slew and output load."
    ],
    "exercise": "Choose Cell transistors and compare typical, slow and fast device corners. Why are rise and fall delays different from each other and from the ideal zero-delay logic check?"
  },
  "stages": [
    {
      "id": "logic",
      "label": "Logic check",
      "status": "available",
      "reason": "Fast ideal zero-delay evaluation of the published explicit cell connections and testbench checks. No synthesis, RTL interpretation, transistor voltages, device corners or physical delay is modeled.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "Structural cell example",
          "url": "/digital/logic-inverter/cells.v"
        },
        {
          "kind": "json",
          "label": "Stimuli and assertions",
          "url": "/digital/logic-inverter/testbench.json"
        }
      ]
    },
    {
      "id": "transistor",
      "label": "Cell transistors",
      "status": "available",
      "reason": "Live browser ngspice/WebAssembly transient simulation of IHP standard-cell transistors. The included example netlist is hand-written; a separate browser Yosys run generates the post-synthesis netlist. No routed parasitics, static timing closure, DRC/LVS or silicon proof.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "Structural cell example",
          "url": "/digital/logic-inverter/cells.v"
        },
        {
          "kind": "json",
          "label": "Stimuli and assertions",
          "url": "/digital/logic-inverter/testbench.json"
        }
      ],
      "corners": [
        {
          "id": "typ",
          "label": "typ: 1.2 V, 25 \u00b0C"
        },
        {
          "id": "slow",
          "label": "slow: 1.08 V, 125 \u00b0C"
        },
        {
          "id": "fast",
          "label": "fast: 1.32 V, -40 \u00b0C"
        }
      ]
    },
    {
      "id": "rtl",
      "label": "RTL",
      "status": "unavailable",
      "reason": "Synthesizable source is provided. No standalone browser RTL event simulator is bundled.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "RTL source",
          "url": "/digital/logic-inverter/rtl.v"
        }
      ]
    },
    {
      "id": "gate-delay",
      "label": "Gate delays",
      "status": "available",
      "reason": "Event-driven simulation of the synthesized cells with IHP Liberty delay-table interpolation, fanout capacitance and external output loads. Fixed slew at all cell inputs; maximum delay over arcs per output, not sensitized-path timing. No wire delays, setup/hold checks, SDF annotation or STA.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "RTL source",
          "url": "/digital/logic-inverter/rtl.v"
        }
      ],
      "corners": [
        {
          "id": "typ",
          "label": "typ: 1.2 V, 25 \u00b0C"
        },
        {
          "id": "slow",
          "label": "slow: 1.08 V, 125 \u00b0C"
        },
        {
          "id": "fast",
          "label": "fast: 1.32 V, -40 \u00b0C"
        }
      ]
    },
    {
      "id": "timing",
      "label": "SPICE \u00b7 mapped cells",
      "status": "available",
      "reason": "After the separate browser Yosys synthesis action, ngspice simulates the mapped IHP cell transistors. Every simulation runs fresh; the mapping stays in this tab. Detailed runs may take tens of seconds. Not SDF simulation, STA or post-layout timing.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "Synthesizable RTL",
          "url": "/digital/logic-inverter/rtl.v"
        }
      ],
      "corners": [
        {
          "id": "typ",
          "label": "typ: 1.2 V, 25 \u00b0C"
        },
        {
          "id": "slow",
          "label": "slow: 1.08 V, 125 \u00b0C"
        },
        {
          "id": "fast",
          "label": "fast: 1.32 V, -40 \u00b0C"
        }
      ]
    }
  ],
  "cells": [
    {
      "name": "sg13g2_inv_1",
      "count": 1
    }
  ],
  "cellCount": 1,
  "cellAreaUm2": 5.4432,
  "instances": [
    {
      "type": "sg13g2_inv_1",
      "name": "u_inv",
      "connections": {
        "Y": "Y",
        "A": "A"
      }
    }
  ],
  "simulation": {
    "inputs": [
      {
        "name": "A",
        "transitions": [
          [
            0,
            0
          ],
          [
            10,
            1
          ],
          [
            20,
            0
          ],
          [
            30,
            1
          ]
        ]
      }
    ],
    "output": "Y",
    "outputWidth": 1,
    "endTimeNs": 40,
    "transitionNs": 0.1,
    "outputLoadFf": 10,
    "maxStepNs": 0.005,
    "checks": [
      {
        "timeNs": 2,
        "expected": "1"
      },
      {
        "timeNs": 12,
        "expected": "0"
      },
      {
        "timeNs": 22,
        "expected": "1"
      },
      {
        "timeNs": 32,
        "expected": "0"
      }
    ]
  },
  "top": "logic_inverter_rtl",
  "rtl": "// AiSIC synthesizable teaching RTL.\n`timescale 1ns/1ps\nmodule logic_inverter_rtl (input A, output Y);\n  assign Y = ~A;\nendmodule\n",
  "cellNetlist": "// Hand-written IHP structural example; not a synthesis output.\nmodule logic_inverter_cells (input A, output Y);\n\n  sg13g2_inv_1 u_inv (.Y(Y), .A(A));\nendmodule\n",
  "resources": {
    "record": "/digital/logic-inverter/design.json",
    "rtl": "/digital/logic-inverter/rtl.v",
    "testbench": "/digital/logic-inverter/testbench.json",
    "netlist": "/digital/logic-inverter/cells.v",
    "page": "/digital.html#logic-inverter",
    "schema": "/schemas/digital-design.schema.json",
    "urlBase": "Resource URLs start at this site's root."
  },
  "evidence": {
    "pdkCommit": "68c1265b1c4e5e1b4613bef34b9ce7bfe4b2c957",
    "libraryFiles": {
      "typ": {
        "url": "/digital/library/sg13g2_stdcell_typ_1p20V_25C.lib",
        "sha256": "7677a8918689f452e80405ad16a83e744709342574f2aedcc507c2758986b396",
        "voltage": 1.2,
        "temperatureC": 25
      },
      "slow": {
        "url": "/digital/library/sg13g2_stdcell_slow_1p08V_125C.lib",
        "sha256": "1ac6a0301184b3a8aa1a4a01910967f624c8e869517777f529985f11f04588c3",
        "voltage": 1.08,
        "temperatureC": 125
      },
      "fast": {
        "url": "/digital/library/sg13g2_stdcell_fast_1p32V_m40C.lib",
        "sha256": "f191a3132d0f2f59ca2721884cdb1d8360c8fbf3e0012056af62583dd69ae701",
        "voltage": 1.32,
        "temperatureC": -40
      }
    },
    "sourceHashes": {
      "rtl.v": "77c6154539a1e6199e8c94a18427154a80fd0b23ca04b23719c25cbb885679d0",
      "cells.v": "cc4c0894e2d70e861dec93a05b72248bf9dd163508a1f3241db14ebe0ee07836",
      "testbench.json": "8182dcbfad844ea128e7a7a4dc82084108114041097c7c57f11dd28c1691c7b0"
    }
  },
  "qualification": {
    "status": "demonstration-tests-only",
    "analogStudyIncluded": false,
    "delayLimits": "informational",
    "note": "Each browser run checks its finite truth-table or sequence. These new digital designs have not completed the 11-corner and 40-seed analog qualification protocol."
  },
  "boundary": "Fast mode checks ideal zero-delay behavior of the published explicit cells; it is not RTL simulation or physical timing. Detailed modes simulate IHP cell transistors, directly or after browser Yosys synthesis. No routed parasitics, static timing closure, DRC/LVS or silicon proof.",
  "recordVersion": 1,
  "entryType": "library-block",
  "group": "Digital logic",
  "subgroup": "Combinational logic",
  "kind": "combinational",
  "reference": null,
  "implementation": {
    "kind": "standard-cell-reference",
    "evidence": "transistor-simulation",
    "purpose": "A small digital block for learning, reuse and retargeting; not a claim of optimal implementation.",
    "netlistBoundary": "The included structural example is hand-written. Browser synthesis generates a separate cell netlist, and simulation adds ideal stimuli, supply and loads.",
    "physicalSignoff": "No placed/routed layout, extracted interconnect, DRC/LVS or silicon measurements."
  },
  "diagram": {
    "schema": "aisic.diagram/1",
    "kind": "cell-connectivity",
    "representation": "explicit-cell-example",
    "ports": [
      {
        "id": "A",
        "name": "A",
        "direction": "input",
        "width": 1,
        "nets": [
          "A"
        ]
      },
      {
        "id": "Y",
        "name": "Y",
        "direction": "output",
        "width": 1,
        "nets": [
          "Y"
        ]
      }
    ],
    "nodes": [
      {
        "id": "u_inv",
        "kind": "logic-cell",
        "cell": "sg13g2_inv_1",
        "family": "inv",
        "sequential": false,
        "ports": [
          {
            "name": "Y",
            "direction": "output",
            "net": "Y"
          },
          {
            "name": "A",
            "direction": "input",
            "net": "A"
          }
        ],
        "powerPorts": [
          {
            "name": "VDD",
            "net": "vdd"
          },
          {
            "name": "VSS",
            "net": "0"
          }
        ]
      }
    ],
    "nets": [
      {
        "id": "A",
        "endpoints": [
          {
            "node": "$ports",
            "port": "A",
            "bit": 0,
            "role": "driver"
          },
          {
            "node": "u_inv",
            "port": "A",
            "role": "sink"
          }
        ]
      },
      {
        "id": "Y",
        "endpoints": [
          {
            "node": "$ports",
            "port": "Y",
            "bit": 0,
            "role": "sink"
          },
          {
            "node": "u_inv",
            "port": "Y",
            "role": "driver"
          }
        ]
      }
    ],
    "powerNets": [
      {
        "id": "vdd",
        "role": "supply"
      },
      {
        "id": "0",
        "role": "ground"
      }
    ],
    "scope": "Logical connectivity of the explicit cell example; power connections are listed separately. Not the synthesized result or a physical layout."
  },
  "ports": [
    {
      "id": "A",
      "name": "A",
      "direction": "input",
      "width": 1,
      "nets": [
        "A"
      ]
    },
    {
      "id": "Y",
      "name": "Y",
      "direction": "output",
      "width": 1,
      "nets": [
        "Y"
      ]
    }
  ],
  "authoring": {
    "schema": "aisic.authoring/1",
    "source": "/digital/logic-inverter/design.json",
    "canonicalFields": [
      "name",
      "summary",
      "lesson",
      "boundary",
      "group",
      "subgroup",
      "reference",
      "implementation",
      "qualification"
    ],
    "explanationField": "lesson",
    "unknownFields": "preserved",
    "generatedFields": [
      "schema",
      "recordVersion",
      "entryType",
      "id",
      "domain",
      "technology",
      "kind",
      "ports",
      "stages",
      "cells",
      "cellCount",
      "cellAreaUm2",
      "instances",
      "simulation",
      "top",
      "rtl",
      "cellNetlist",
      "resources",
      "evidence",
      "diagram",
      "authoring",
      "generated"
    ],
    "generatedStageFields": [
      "id",
      "status",
      "artifacts",
      "corners"
    ],
    "generatedResourceFields": [
      "record",
      "page",
      "rtl",
      "testbench",
      "netlist",
      "schema",
      "urlBase"
    ],
    "note": "Edit the lesson only here; it is the explanation used by people and AI. The data builder preserves authored fields and unknown extensions. Numerical recipes remain in tools/digital_flow.py."
  },
  "generated": {
    "schema": "aisic.generated/1",
    "builder": "tools/digital_flow.py",
    "builderSha256": "3aa880c92a73d16c6e3e2787d6a6145aa2705f273c8664493eb627c67c127a6a",
    "authoredSha256": "00fd6df5e77c5ebe5a89d842cedd7f8f20f0ac660c5aeb80dbd9fdd5dd536e0d",
    "diagramSha256": "bc1f8af2bf8c9296fcdf73495ff86918818b63d44ec47fd8a7bd240692a3f29d",
    "numericalSha256": "85807d8448dd4cf08b6321157d9a3fef7f92d35e515f4ee3ed24277c728145e3",
    "evidencePolicy": "This data build does not run simulations or certify existing evidence. Compare source fingerprints before reusing results."
  }
}