{
  "schema": "aisic.digital-design/1",
  "id": "logic-nand2",
  "name": "NAND gate",
  "domain": "digital",
  "technology": "IHP SG13G2 130 nm",
  "summary": "A two-input universal gate, checked against all four input combinations.",
  "lesson": {
    "idea": "Y is low only when A and B are high. NAND is universal: combinations of NAND gates can realize any Boolean function.",
    "steps": [
      "Enumerate all four Boolean input combinations.",
      "Map the function explicitly to one NAND2 cell.",
      "Inspect output transitions after input changes."
    ],
    "tradeoffs": [
      "Input-to-output timing can differ between pins because the transistor paths differ.",
      "This truth-table test checks logic, not noise margins or transistor-level power."
    ],
    "exercise": "Build an inverter by tying the NAND inputs together. What changes in input load?"
  },
  "stages": [
    {
      "id": "logic",
      "label": "Logic check",
      "status": "available",
      "reason": "Fast ideal zero-delay evaluation of the published explicit cell connections and testbench checks. No synthesis, RTL interpretation, transistor voltages, device corners or physical delay is modeled.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "Structural cell example",
          "url": "/digital/logic-nand2/cells.v"
        },
        {
          "kind": "json",
          "label": "Stimuli and assertions",
          "url": "/digital/logic-nand2/testbench.json"
        }
      ]
    },
    {
      "id": "transistor",
      "label": "Cell transistors",
      "status": "available",
      "reason": "Live browser ngspice/WebAssembly transient simulation of IHP standard-cell transistors. The included example netlist is hand-written; a separate browser Yosys run generates the post-synthesis netlist. No routed parasitics, static timing closure, DRC/LVS or silicon proof.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "Structural cell example",
          "url": "/digital/logic-nand2/cells.v"
        },
        {
          "kind": "json",
          "label": "Stimuli and assertions",
          "url": "/digital/logic-nand2/testbench.json"
        }
      ],
      "corners": [
        {
          "id": "typ",
          "label": "typ: 1.2 V, 25 \u00b0C"
        },
        {
          "id": "slow",
          "label": "slow: 1.08 V, 125 \u00b0C"
        },
        {
          "id": "fast",
          "label": "fast: 1.32 V, -40 \u00b0C"
        }
      ]
    },
    {
      "id": "rtl",
      "label": "RTL",
      "status": "unavailable",
      "reason": "Synthesizable source is provided. No standalone browser RTL event simulator is bundled.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "RTL source",
          "url": "/digital/logic-nand2/rtl.v"
        }
      ]
    },
    {
      "id": "gate-delay",
      "label": "Gate delays",
      "status": "available",
      "reason": "Event-driven simulation of the synthesized cells with IHP Liberty delay-table interpolation, fanout capacitance and external output loads. Fixed slew at all cell inputs; maximum delay over arcs per output, not sensitized-path timing. No wire delays, setup/hold checks, SDF annotation or STA.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "RTL source",
          "url": "/digital/logic-nand2/rtl.v"
        }
      ],
      "corners": [
        {
          "id": "typ",
          "label": "typ: 1.2 V, 25 \u00b0C"
        },
        {
          "id": "slow",
          "label": "slow: 1.08 V, 125 \u00b0C"
        },
        {
          "id": "fast",
          "label": "fast: 1.32 V, -40 \u00b0C"
        }
      ]
    },
    {
      "id": "timing",
      "label": "SPICE \u00b7 mapped cells",
      "status": "available",
      "reason": "After the separate browser Yosys synthesis action, ngspice simulates the mapped IHP cell transistors. Every simulation runs fresh; the mapping stays in this tab. Detailed runs may take tens of seconds. Not SDF simulation, STA or post-layout timing.",
      "artifacts": [
        {
          "kind": "verilog",
          "label": "Synthesizable RTL",
          "url": "/digital/logic-nand2/rtl.v"
        }
      ],
      "corners": [
        {
          "id": "typ",
          "label": "typ: 1.2 V, 25 \u00b0C"
        },
        {
          "id": "slow",
          "label": "slow: 1.08 V, 125 \u00b0C"
        },
        {
          "id": "fast",
          "label": "fast: 1.32 V, -40 \u00b0C"
        }
      ]
    }
  ],
  "cells": [
    {
      "name": "sg13g2_nand2_1",
      "count": 1
    }
  ],
  "cellCount": 1,
  "cellAreaUm2": 7.2576,
  "instances": [
    {
      "type": "sg13g2_nand2_1",
      "name": "u_nand",
      "connections": {
        "Y": "Y",
        "A": "A",
        "B": "B"
      }
    }
  ],
  "simulation": {
    "inputs": [
      {
        "name": "A",
        "transitions": [
          [
            0,
            0
          ],
          [
            20,
            1
          ],
          [
            40,
            0
          ],
          [
            60,
            1
          ]
        ]
      },
      {
        "name": "B",
        "transitions": [
          [
            0,
            0
          ],
          [
            10,
            1
          ],
          [
            20,
            0
          ],
          [
            30,
            1
          ],
          [
            40,
            0
          ],
          [
            50,
            1
          ],
          [
            60,
            0
          ],
          [
            70,
            1
          ]
        ]
      }
    ],
    "output": "Y",
    "outputWidth": 1,
    "endTimeNs": 80,
    "transitionNs": 0.1,
    "outputLoadFf": 10,
    "maxStepNs": 0.005,
    "checks": [
      {
        "timeNs": 2,
        "expected": "1"
      },
      {
        "timeNs": 12,
        "expected": "1"
      },
      {
        "timeNs": 22,
        "expected": "1"
      },
      {
        "timeNs": 32,
        "expected": "0"
      },
      {
        "timeNs": 42,
        "expected": "1"
      },
      {
        "timeNs": 52,
        "expected": "1"
      },
      {
        "timeNs": 62,
        "expected": "1"
      },
      {
        "timeNs": 72,
        "expected": "0"
      }
    ]
  },
  "top": "logic_nand2_rtl",
  "rtl": "// AiSIC synthesizable teaching RTL.\n`timescale 1ns/1ps\nmodule logic_nand2_rtl (input A, B, output Y);\n  assign Y = ~(A & B);\nendmodule\n",
  "cellNetlist": "// Hand-written IHP structural example; not a synthesis output.\nmodule logic_nand2_cells (input A, B, output Y);\n\n  sg13g2_nand2_1 u_nand (.Y(Y), .A(A), .B(B));\nendmodule\n",
  "resources": {
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    "testbench": "/digital/logic-nand2/testbench.json",
    "netlist": "/digital/logic-nand2/cells.v",
    "page": "/digital.html#logic-nand2",
    "schema": "/schemas/digital-design.schema.json",
    "urlBase": "Resource URLs start at this site's root."
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  "evidence": {
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        "voltage": 1.2,
        "temperatureC": 25
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        "voltage": 1.08,
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      "fast": {
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        "voltage": 1.32,
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  },
  "qualification": {
    "status": "demonstration-tests-only",
    "analogStudyIncluded": false,
    "delayLimits": "informational",
    "note": "Each browser run checks its finite truth-table or sequence. These new digital designs have not completed the 11-corner and 40-seed analog qualification protocol."
  },
  "boundary": "Fast mode checks ideal zero-delay behavior of the published explicit cells; it is not RTL simulation or physical timing. Detailed modes simulate IHP cell transistors, directly or after browser Yosys synthesis. No routed parasitics, static timing closure, DRC/LVS or silicon proof.",
  "recordVersion": 1,
  "entryType": "library-block",
  "group": "Digital logic",
  "subgroup": "Combinational logic",
  "kind": "combinational",
  "reference": null,
  "implementation": {
    "kind": "standard-cell-reference",
    "evidence": "transistor-simulation",
    "purpose": "A small digital block for learning, reuse and retargeting; not a claim of optimal implementation.",
    "netlistBoundary": "The included structural example is hand-written. Browser synthesis generates a separate cell netlist, and simulation adds ideal stimuli, supply and loads.",
    "physicalSignoff": "No placed/routed layout, extracted interconnect, DRC/LVS or silicon measurements."
  },
  "diagram": {
    "schema": "aisic.diagram/1",
    "kind": "cell-connectivity",
    "representation": "explicit-cell-example",
    "ports": [
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        "name": "Y",
        "direction": "output",
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        "nets": [
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    ],
    "nodes": [
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        "id": "u_nand",
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        "family": "nand2",
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        "role": "supply"
      },
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        "role": "ground"
      }
    ],
    "scope": "Logical connectivity of the explicit cell example; power connections are listed separately. Not the synthesized result or a physical layout."
  },
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