About AiSIC

Understand a circuit. Build on its reasoning.

AiSIC is a shared reference for people learning or designing circuits, and for AI systems helping with that work. The aim is a reasonable implementation whose purpose, assumptions and trade-offs are easy to inspect.

One site, different ways to learn.

Start with a block, learn a design method, or follow a complete project.

Library

Browse Analog, Digital and Mixed-signal blocks. Explanations and learning experiments stay beside each block, along with its circuit, testbenches and reusable records. The digital workspace offers fast zero-delay logic checks, plus browser-local synthesis and detailed IHP cell-transistor simulation when physical delay matters.

Methodology

Learn the steps behind a design, starting with NMOS characterization and the transconductance-efficiency, or g_m/I_D, method. Carry the method into a new technology with fresh device data.

Showcase

Follow documented project choices, contributions, results and lessons. Projects may be human-designed, AI-assisted or a combination. No showcase projects have been published yet.

Useful to read.
Useful to build on.

Plain-language explanations introduce the purpose and mechanism. Equations state their assumptions. Testbenches make numerical claims checkable, and structured records let AI systems inspect the same design intent.

AI is optional. Documented choices and evidence matter whether a person, an AI system, or both helped produce a design.

A starting point,
not a universal optimum.

The reference circuits aim to be reasonable and understandable. They are not claimed to be the fastest, smallest or lowest-power implementation for every application.

Reusing an idea in another technology means revisiting device choices, voltage limits, dimensions, bias, matching, loading and layout. The original sizing and simulated performance do not transfer as guarantees.

Read the evidence in context

What the library does—and does not—establish.

The current transistor-level reference circuits use IHP SG13G2 device models. Results apply to the stated design, testbench and simulation conditions.

Transistor design: The transistor-level circuit is the design. A behavioral model is a separate approximation for understanding or system simulation, not a replacement implementation.
Simulation checks: Nominal runs, process/voltage/temperature corners and Monte Carlo draws test the declared limits under specified conditions. A finite set of passing runs is not a manufacturing-yield guarantee.
Learning experiments: Changing a parameter helps reveal a relationship or trade-off. An exercise is not a newly qualified design point; inspect the resulting behavior and limits again.
Physical implementation: Testbenches may include ideal stimuli, loads and bias sources. A fabricated implementation needs its surrounding circuitry, layout, extraction and appropriate reliability and physical checks. The site does not establish physical signoff or measured-silicon performance for every block.

Your simulations stay in your browser.

Analog and digital workspaces keep completed runs in the current page. To keep them after leaving or reloading, open Saved runs at the bottom and choose Save on this device. Saving is optional and off until you choose it; simulation results are not uploaded.

Device saving uses this site's browser storage (IndexedDB), with a small local preference. It keeps up to 20 runs for 7 days, within 50 MiB total and 12 MiB per run. Oldest runs are removed first. You can export a run, clear saved results, or stop saving and delete them in the same panel. Browser clearing or eviction can also remove them; export important results.

A restored run is dated and must match the design, settings and implementation. It is not a new simulation. The bottom Log panel shows running phases and elapsed time; a moving indicator means work is active, not a promised completion percentage.

The reasoning should travel with the circuit.

In the Library, open Use this circuit to get the block's default JSON record or download a JSON record of your current edited design. Each record includes its design, assumptions and testbenches. Keep limits and evidence attached when reusing a record. Check the applicable licences before redistributing code, device models or project artifacts.