Methodology / Analog design
From device curves to design decisions.
Understand the transistor before sizing the circuit. Generate NMOS curves with real IHP SG13G2 models, then use transconductance efficiency to connect gain, current and device width.
01 / Measure the device
NMOS device laboratory
A low-voltage NMOS, with its source and bulk grounded. The gate and drain are driven by ideal voltage sources. These are DC model simulations, not silicon measurements.
How to read the curves · sweep conditions
What stays fixed?
For the gate sweep, VGS runs from 0 to 1.2 V while VDS, W, temperature and corner stay fixed. VSB is always 0 V. For the output curves, VDS sweeps from 0 to 1.2 V at five gate voltages, using your selected L.
How to read the curves
- ID versus VGS
- The gate controls conduction. A logarithmic current axis reveals the low-current region as well as strong conduction.
- ID versus VDS
- The output curve shows drain-bias sensitivity. A flatter part has smaller gds; saturation does not make the current perfectly constant.
- gm/ID
- Small-signal transconductance per unit bias current, in V−1. It is an efficiency measure—not voltage gain.
- ID/W and gm/gds
- Current per width helps estimate size. Intrinsic gain is a single-device estimate; a real amplifier also depends on its load and topology.
Inputs changed. These curves still show the conditions above; generate curves again to update them.
Extraction, numerical limits and reproducibility
Drain current is −I(Vd), the current entering the device drain. gm is dID/dVGS from a 2 mV sweep using centred differences (one-sided at the plotted endpoints). gds uses two identical devices at VDS ± 1 mV. These are numerical terminal derivatives, not simulator-internal parameters.
Efficiency ratios omit endpoints, ID below 1 nA and non-positive gm. Intrinsic-gain plots also omit gds ≤ 1 pS. These numerical exclusions do not define inversion-region boundaries. Small current and small derivatives can be sensitive to resolution and leakage.
Width is the total drawn width; the library automatically applies its finger rule. Changing width can change the model's current density, parasitics and finger count. These curves contain no capacitance, noise, mismatch or reliability characterization.
JSON includes all points, conditions, derivative settings and experiment netlists. Run exported decks with ngspice and the PSP103 OSDI model, with the model card saved beside them. Model-card licence: Apache 2.0.
02 / Turn curves into a first sizing
The gm/ID methodology
Choose the operating point using simulated device data, rather than relying on a square-law approximation everywhere. The method transfers between technologies; the numerical curves do not.
Start from the circuit requirement
Estimate the transconductance you need. For a simple single-stage, dominant-pole amplifier driving a capacitive load, gm ≈ 2πfuCL is a starting estimate. This is the effective stage transconductance: use the topology to relate it to each transistor's gm. It is not a general formula for compensated, multi-stage amplifiers.
Choose efficiency and length together
Read gm/ID at a realistic drain bias. Higher efficiency generally means lower current density and more width for a given current. Lower efficiency often trades more current for smaller devices and potentially higher speed. Check capacitances, noise and headroom separately. There are no universal numeric boundaries between weak, moderate and strong inversion.
ID = gm / (gm/ID)
Read current per width
At the same length and bias conditions, use the ID/W curve to estimate a width. VGS comes from the corresponding operating point, not a guessed threshold voltage.
W ≈ ID,target / (ID/W)lookup
Width scaling is an initial estimate. Re-simulate at the new width and finger arrangement, especially with narrow devices.
Close the loop in the actual circuit
Check bias, swing, gain, stability, speed, noise and matching. Each device's actual drain and body biases matter. Larger width adds capacitance, so current efficiency does not guarantee bandwidth or settling. Recheck corners, temperature and supply; then verify layout and extracted parasitics. A device lookup does not qualify the surrounding circuit.
Try a sizing estimate
Uses the selected-length curve from your last completed simulation. It interpolates adjacent valid points and never extrapolates. Enter the required transconductance of one transistor; its drain current is not the circuit's total supply current or a differential pair's tail current.
Generate device curves first.
Try this: keep W = 5 µm and VDS = 0.6 V, compare the lengths, then lower VDS. Does the same efficiency still provide the same intrinsic gain? Check the actual model response rather than assuming “longer is always better.”
Apply the reasoning to a common-source amplifier, differential pair or five-transistor OTA. Each block keeps its own explanation, sizing decisions and simulation exercises.
Further reading: P. G. A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables (2017). Device models: IHP Open PDK. This laboratory generates its own curves from the locally supplied model cards.