Chopper OTA, a CM loop for each stage

How it works

The chopper amplifier's OTA with a common-mode loop for each stage. The signal path is the core's: a PMOS pair into a folded cascode, a chopper between the stages held straight in every bench here, and a Miller-compensated common-source stage. The first stage's outputs o1, o2 are sensed at the gates of two NMOS pairs - no resistor loads them - against vr1, the gate voltage a copy of M11's unit takes at Ib; the outputs are averaged by resistors and held at vocm by two of the four copies of each output source.

The testbench draws Ib = 5 µA out of the diode MB. MT is two copies of it (10 µA); MB1 copies Ib into the NMOS diode MB2, which M3 and M4 copy twice (10 µA each). The cascode gates come from long, narrow diodes carrying Ib: MB6 stands one cascode V_GS plus about 0.2 V above ground, the room M3 needs under M5, and MB3 likewise leaves M7 room under M9 - differences that grow with temperature, as V_DSAT does, where a poly resistor's drop would shrink. The stage-1 loop holds o1 and o2 at vr1, the gate voltage M11 needs for N2·Ib = 20 µA, about 0.5 V, close to where its V_GS stops moving with temperature. M13, M14 are N2 − 2 copies of MB and M15, M16 two copies of MC4, which carries Ib when the output loop is balanced; the output loop trims only what M11 carries beyond what M13 sources.

Signal path

• Input pair (M1, M2, MT): MT's 10 µA divides between M1 and M2 as the inputs differ; a rise on inp takes current away from the fold node f1.
• Folded cascode (M3, M4, M5, M6, M7, M8, M9, M10): M3, M4 sink 2·Ib each; what the pair does not supply there is drawn through the NMOS cascodes M5, M6 from o1, o2, where the loads M7, M8 under the PMOS cascodes M9, M10 source Ib. Cascoded on both sides, o1 and o2 are the amplifier's high-resistance nodes, and a rise on inp pulls o1 down.
• Output chopper (SO1, SO2, SO3, SO4): With clk high, SO1 and SO2 join o1 to g1 and o2 to g2; clocked, SO3 and SO4 cross them every other half period, so a chopped signal returns to baseband at g1, g2 while the first stage's offset and 1/f noise leave at the chopping frequency. Every bench of this OTA holds it straight.
• Second stage (M11, M12, M13, M14, CC1, CC2, RZ1, RZ2): M11, M12 invert g1, g2 onto outp, outn against the sources M13, M14, so outp follows inp. CC1, CC2 across them, in series with RZ1, RZ2, make g1, g2 the dominant pole.
• Stage-1 reference (MR1, MR2): MR1 feeds Ib into MR2, one unit of M11: vr1 is the gate voltage at which M11, N2 units, carries N2·Ib.
• Stage-1 common-mode loop (MD1, MD2, MD3, MD4, MD5, MD6, MD7, MD8): Each pair compares one of o1, o2 with vr1 around its own tail (MD5, MD6); the reference sides MD2, MD4 feed the diode MD8, which M7, M8 copy. A rising o1, o2 common mode steers current into MD1, MD3, MD8 and the loads carry less, and o1, o2 fall back to vr1.
• Output common-mode loop (RM1, RM2, CM1, CM2, MC1, MC2, MC3, MC4, MC5, M15, M16): RM1, RM2 and CM1, CM2 average the outputs onto cms; MC1 compares it with vocm on MC2. MC4, on the reference side, is copied twice by M15 and M16: a rising output common mode turns MC2 and with it M15, M16 down, and the outputs fall.

Key relations

• Differential gain: A_d ≈ g_m1·R_o1·g_m11·(r_o11 ∥ r_o13). R_o1 is the cascoded resistance at o1, set mostly by the NMOS side (g_m5·r_o5·r_o3); about 78 dB with the chopper held.
• Unity-gain frequency: ω_u ≈ g_m1/C_c. About 4.5 MHz: g_m1 ≈ 92 µS, C_c = 3 pF. The closed-loop response depends on the feedback network; the complete clocked amplifier must settle within each half-period at its selected gain and chopping frequency.
• Compensation zero: ω_z = 1/[C_c·(R_z − 1/g_m11)]. R_z = 12 kΩ is above 1/g_m11 ≈ 7 kΩ, so the zero lies in the left half-plane, near 11 MHz, and adds phase at ω_u: the margin is close to 90°.
• Headroom under o1: V_GS,11 ≥ V_DS,3 + V_DS,5. About 0.5 V against 0.2 V for M3 and 0.3 V for M5, both near weak inversion, where V_DSAT is about 4kT/q.
• Stage-1 level: V_o1,cm → V_r1 = V_GS,MR2(I_b). A replica, not a fixed voltage: M11 carries N2·Ib at every corner, within the few percent its larger V_DS adds.
• Output common mode: V_oc → V_ocm. Within about 25 mV: the output loop's small gain leaves the error of the few-percent current it must trim.
• Two loops, one stage: t_s,cm ≈ 0.66 µs typical, 2.4 µs slow, hot, low supply. The loops meet at the second stage: a step on vocm moves M11's current through its r_o, which the output loop must supply while the first loop holds o1 - one slow exponential, no overshoot.

Trade-offs

• Miller capacitor (Cc): larger adds margin for a heavier feedback network, but slows the OTA and its recovery after each chopper edge.
• Second-stage current (N2): more raises g_m11, the output pole and the slew rate into the load, at the supply's cost; o1, o2 do not move, since M11's unit sets them.
• Stage-1 sense pairs (Wd, Ld): wide pairs in weak inversion stand a low V_GS below o1, leaving their tails room at every corner; long ones match better but load o1, o2 with more gate capacitance.
• Output loop's share of the sources (M15, M16): more copies make the output loop faster and more accurate but let it fight the first loop for the second stage; fewer leave it slow and overdamped.

Testbenches and limits

• Operating point, chopper held: The amplifier as a fully differential follower at its input common mode, its chopper held straight: the current it draws, where its outputs sit, and the difference they settle at with no input.
• Open-loop gain, chopper held: Differential gain and phase with the follower's loop closed only at DC, through a 1 TH coil: every frequency the sweep visits sees the open loop, and the operating point is the follower's. The chopper is held straight.
• Step response, chopper held: A 200mV differential step into the follower, its chopper held: how fast the output difference follows and whether it rings - the test that finds a local loop an open-loop phase margin hides.
• Common-mode loop, chopper held: A 50 mV step on the common-mode reference: the output common mode has to follow it, and how it gets there - its settling and its overshoot - is the common-mode loop's phase margin, a loop the differential benches never see.
• Noise, chopper held: Noise referred to the differential input of the follower, its chopper held: the density at 1 kHz and the total from 1 Hz to 1 MHz. Held, the first stage's 1/f noise is all here; clocked, the chopper moves it up to the chopping frequency.

Design variables and defaults

Ports

• inp input
• inn input
• outp output
• outn output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin
• vocm bias: the output common mode the output loop holds
• clk clock: high: the output chopper straight
• clkb clock: high: the output chopper crossed

Reference

Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa, A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes, 2011. IEEE Journal of Solid-State Circuits, 46(7):1534-1543.

The OTA's architecture: a PMOS-input folded cascode, the output chopper between the stages, a Miller-compensated second stage. The two common-mode loops - the first stage sensed at transistor gates against a replica of the second stage's gate, the output trimming two copies of each source - and all the sizing are this library's.