Folded-cascode two-stage op amp

How it works

A fully differential op amp in two stages: an NMOS-input folded cascode, whose first-stage outputs o1 and o2 give most of the gain, then common-source NMOS stages that give the output swing. Miller capacitors with nulling resistors split the poles. A common-mode loop averages the outputs, compares the average with vocm and sets the first-stage sinks through a diode they copy. Its PMOS reference uses a replica pair at vocm so the bias devices work at the signal tails' drain voltage; the common-mode amplifier uses 3:1 and 2:3 unit ratios to target one Ib in its output diode at nominal balance. Finite gain and random mismatch leave residual common-mode error.

The 10 µA current fed into ib defines the NMOS unit through MB. MT uses four units for the input pair and MTC two for the common-mode pair. MB1 and the two-unit replica MR work at vocm and make the two-unit PMOS reference MB2 see the same drain voltage as the tails; RB sets the remaining drain drop. One-unit branches generate each cascode gate: MB3-RP1-RP2-MB6 for gcp, and MB7-MB8-MB9 for gcn. At common-mode balance, each half of MTC carries Ib; the 3:1 M17/M18 mirror and 2:3 M19/M21 copy chain make M20 carry one Ib, so M9 and M10 sink two Ib each and the outputs settle at vocm.

Signal path

• Bias generation (MB, MB1, MR, MB2, RB, MB3, RP1, RP2, MB6, MB7, MB8, MB9): MB defines the NMOS unit. MB1 and MR reproduce a two-unit tail under vocm and load the PMOS reference MB2 at the signal branches' drain voltage; RB places its drain. MB3 with RP1/RP2 and MB6 generates gcp, while MB7 into the stacked diodes MB8/MB9 generates gcn.
• Input pair (M1, M2, MT): MT's 4 Ib splits between the fold nodes f1 and f2 in proportion to the differential input; a rise on inp draws more from f1.
• Folded cascode (M3, M4, M5, M6, M7, M8, M9, M10): M3 and M4 feed each fold node 4 Ib; what the pair leaves runs through the PMOS cascodes M5, M6 into o1, o2 and down through the NMOS cascodes M7, M8 into the sinks M9, M10, so o1 and o2 see two cascoded resistances in parallel.
• Second stage (M11, M12, M13, M14): M11 and M12 amplify o1 and o2 onto outp and outn against N units of PMOS source each; o1 falls as inp rises, so outp rises.
• Miller compensation (CC1, RZ1, CC2, RZ2): Each capacitor feeds back from an output to its first-stage node through a nulling resistor: the first-stage node becomes the dominant pole, and the resistor moves the capacitor's zero into the left half-plane, onto the output pole.
• Common-mode detector (RS1, RS2, CS1, CS2): The equal resistors put the average of outp and outn on avg; the capacitors across them reduce high-frequency attenuation and phase lag; finite loading still affects the response.
• Common-mode amplifier (MTC, M15, M16, M17, M18, M19, M21, M22, M20): M15 and M16 compare avg with vocm. M17 is a three-unit diode and M18 one copy, so M19 takes the remaining two unit currents; M21 nominally copies one Ib through the level-shift diode M22 into M20; that ideal balance assumes matched devices at suitable drain voltages. M9 and M10 copy M20 twice. As the outputs rise, the loop increases the sinks and brings their average back down.

Key relations

• Differential gain: A_d ≈ g_m1·R_o1·g_m11·(r_o11 ∥ r_o13 ∥ RS1). R_o1 is the cascoded resistance at o1: g_m7·r_o7·r_o9 on the NMOS side in parallel with the PMOS side; avg is a differential ground, so the detector resistors load the outputs.
• Unity-gain frequency: ω_u ≈ g_m1/C_c. C_c is CC1, 2 pF by default.
• Compensation zero: z ≈ 1/(C_c·(R_z − 1/g_m11)). R_z is RZ1; above 1/g_m11 the zero is in the left half-plane, where it offsets the output pole.
• Common-mode balance: I_M18 = I_b/3, I_M19 = 2I_b/3, I_M21 = I_M20 = I_b. M17 has three units against M18's one; M19 has two diode units and M21 copies three. The sink devices M9 and M10 are two copies of M20, so the folded branches balance at two Ib each.
• Common-mode loop crossover: ω_cm ∝ g_m15/C_c. The ratioed current chain drives the two sinks and integrates on the same Miller capacitors as the differential loop: 66° phase margin at tt and at least 61.8° over forty draws.
• Cascode bias: gcp ≈ g3 − I_b R_P; gcn − vss = V_GS,MB8 + V_GS,MB9. The PMOS branch divides R_P into RP1 and RP2. MB7 supplies current to the two stacked NMOS diodes MB8 and MB9, which set gcn; V_DD − V_SG,MB7 is gbp, not gcn. Actual currents, drain dependence and MB8 body effect affect the diode drops.

Trade-offs

• Miller capacitor: larger adds margin to both the differential and the common-mode loop, but lowers both crossovers and the slew rate.
• Nulling resistor: near 1/g_m11 it cancels the right-half-plane zero; larger adds phase lead, but too large pulls the zero below the crossover.
• Detector resistor: larger loads the outputs less, but lengthens the slow tail RS·CS that the common-mode amplifier's gate capacitance leaves on a common-mode step.
• Replica bias: RB moves the PMOS reference's drain voltage; too little drop loses the match to the signal tails, while too much takes MB2 out of saturation at the low-supply corner.
• Common-mode mirror ratios: the 3:1 and 2:3 unit counts are the DC balance, not tuning knobs; changing either moves the output common mode systematically.
• PMOS unit length: longer lowers the fold sources' flicker noise, which dominates the input noise, and adds capacitance at the fold nodes.

Testbenches and limits

• Operating point: The amplifier as a unity-gain differential buffer, its inputs at their common mode: the current it draws, where its output common mode lands against the reference on vocm, and the differential offset.
• Open-loop gain: Differential gain and phase with the loop closed only at DC, through 1 TH inductors, so the operating point is the buffer's and every frequency sees the open loop.
• Common-mode loop gain: Each common-mode loop opened at the break point the circuit brings out, by Middlebrook's double injection - a voltage in series, then a current into the controlled side - with the differential loop closed as in the buffer: the loop's gain, its crossover, and its phase margin.
• Common-mode step: A 50mV step on the output common-mode reference, vocm, with the amplifier a unity-gain differential buffer: the output common mode follows it, and rings if its loop is short of margin.
• Step response: A 400mV differential step into the unity-gain differential buffer: how fast the differential output follows, whether it rings, and how far the output common mode is pushed on the way.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's differential output and its output common mode.
• Common-mode rejection: The same signal on both inputs, on the unity-gain buffer's input common mode: what reaches the differential output is the common-mode to differential gain over the differential one, and what reaches the output common mode is how firmly the common-mode loop holds it.
• Noise: Differential noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.

Design variables and defaults

Ports

• inp input
• inn input
• outp output
• outn output
• vdd supply
• vss ground
• vocm bias: the output common mode asked for
• ib bias: the reference current, fed into this pin
• cmo bias: the common-mode amplifier's output, the diode M20: the testbench joins it to cmg, and breaks the loop there
• cmg bias: the gates of the sinks M9, M10

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd, McGraw-Hill, 2016. Sec. 9.2.4 (folded-cascode op amps), Sec. 9.7 (common-mode feedback) and Sec. 10.5 (compensation of two-stage op amps).

The topology: an NMOS-input folded cascode feeding common-source second stages, Miller compensation with nulling resistors, resistive-capacitive common-mode sensing and an error amplifier that sets the first-stage current sinks. The bias network with its resistor-set cascode drops, the error amplifier's current output into a diode the sinks copy, the sizing and the targets are this library's, for SG13G2 at 1.2 V.