Two-stage OTA, class-AB output

How it works

A low-power fully differential OTA with a class-AB output. A PMOS pair on diode loads is mirrored, with a gain of B, into the cascoded nodes d1 and d2. On each side a driver moves a stack in which two diodes hold the gates of complementary output followers a fixed voltage apart, so the followers idle at a current set by counts of devices, and either can carry far more when the output needs it. A common-mode loop trims the first-stage PMOS sources through a diode it feeds.

The bench draws Ib out of the PMOS diode MB, whose gate every PMOS source shares, so each current is a count of units. MB1 copies it seven times through RN1, RN2 into the NMOS diode MB2, which puts the NMOS cascode gate vcn a fixed drop above vgn; MB3 pulls the same through RP1, RP2 from MB4 for the PMOS cascode gate vcp. MTC copies MB2. The loop sets M31's current until the outputs sit at vocm, 0.6 V by default; at balance both of its pair's drains sit one diode drop below vdd at the same density.

Signal path

• Input pair (MT, M1, M2, M3, M4): MT's 4 Ib splits between the PMOS pair M1, M2, whose n-wells sit on their sources; the diodes M3 and M4 turn each half into a gate voltage.
• Mirrors and cascodes (M5, M6, M7, M8, M9, M10, M11, M12, M13, M14): M5 and M6 copy the diode currents B times through the NMOS cascodes M7, M8 from d1 and d2, which PMOS sources load under the cascodes M13, M14: M9, M10 fixed, M11, M12 set by the common-mode loop.
• Class-AB driver (M21, M15, M17, M19, CC1, RZ1): M21 amplifies d1 against the source M15; the diodes M17 and M19 in between keep gn1 and gp1 a fixed voltage apart; CC1 in series with RZ1 wraps M21 from gp1 back to d1. The other side, M22 with M16, M18, M20, matches.
• Output followers (M23, M25, M24, M26): Complementary source followers: M23 pushes current into outn and M25 pulls it out, each turning on harder as the stack moves its way; M24 and M26 serve outp.
• Common-mode detector (RS1, RS2, CS1, CS2): The resistors average outp and outn onto vsen; the capacitors across them keep the average from lagging.
• Common-mode amplifier (MTC, M27, M28, M29, M30, M31): M27, M28 compare vocm with vsen on the 2:1 mirror M29, M30; the current left, I28 − I27/2, runs into the diode M31, whose copies M11, M12 source more into d1, d2 as the outputs rise, which pulls the outputs back down.

Key relations

• Differential gain: A_d ≈ B·g_m1·R_d·g_m21·R_gp. R_d is the cascoded resistance at d1 and R_gp the driver's output resistance at the stack; the followers pass the result at about one.
• Unity-gain frequency: ω_u ≈ B·g_m1/C_c. C_c is CC1, wrapped around the driver alone.
• Class-AB bias: V_GS23 + V_SG25 = V_GS17 + V_SG19. A translinear loop: the followers are A copies of the diodes and share their source voltage, so they idle at A times the stack current.
• Follower pole and its zero: 1/(R_z·C_c) ≈ (g_m23 + g_m25)/C_L. R_z is RZ1: its zero lands near the followers' output pole, which the Miller capacitor does not enclose.
• Stack headroom: V_DD ≥ V_SD15 + V_GS17 + V_SG19 + V_DS21. Wide diodes and followers in weak inversion keep the middle two small; the driver near its zero-temperature-coefficient point keeps d1 high enough for the mirror and cascode beneath it.

Trade-offs

• Stack current S: more gives the driver the transconductance a small nulling resistor needs, and cleaner large steps, for more supply current.
• Level-shift and follower widths: wider lowers their gate-source voltages, which is what fits the stack in 1.2 V, and adds capacitance at gn1 and gp1.
• Driver width: narrower raises d1, the room the mirror and its cascode share, and raises the driver's own saturation voltage against gp1.
• Miller capacitor: larger adds margin and slows the slew; the nulling resistor must follow the followers' output pole.

Testbenches and limits

• Operating point: The amplifier as a unity-gain differential buffer, its inputs at their common mode: the current it draws, where its output common mode lands against the reference on vocm, and the differential offset.
• Open-loop gain: Differential gain and phase with the loop closed only at DC, through 1 TH inductors, so the operating point is the buffer's and every frequency sees the open loop.
• Common-mode loop gain: Each common-mode loop opened at the break point the circuit brings out, by Middlebrook's double injection - a voltage in series, then a current into the controlled side - with the differential loop closed as in the buffer: the loop's gain, its crossover, and its phase margin.
• Common-mode step: A 50mV step on the output common-mode reference, vocm, with the amplifier a unity-gain differential buffer: the output common mode follows it, and rings if its loop is short of margin.
• Step response: A 200mV differential step into the unity-gain differential buffer: how fast the differential output follows, whether it rings, and how far the output common mode is pushed on the way.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's differential output and its output common mode.
• Common-mode rejection: The same signal on both inputs, on the unity-gain buffer's input common mode: what reaches the differential output is the common-mode to differential gain over the differential one, and what reaches the output common mode is how firmly the common-mode loop holds it.
• Noise: Differential noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.

Design variables and defaults

Ports

• inp input
• inn input
• outp output
• outn output
• vdd supply
• vss ground
• vocm bias: the output common mode asked for
• ib bias: the reference current, drawn out of this pin
• cmo bias: the common-mode amplifier's output, the diode M31: the testbench joins it to cmg, and breaks the loop there
• cmg bias: the gates of the sources M11, M12 the loop sets

Reference

Y.-P. Hsu, Z. Liu, M. M. Hella, A 1.8 uW -65 dB THD ECG Acquisition Front-End IC Using a Bandpass Instrumentation Amplifier With Class-AB Output Configuration, 2018. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(12):1859-1863.

The topology: a PMOS pair with diode loads mirrored with gain into cascoded nodes, a common-source driver moving a two-diode level shifter whose ends drive complementary source followers, PMOS devices of the class-AB stack in wells on their own sources, and a five-transistor error amplifier that sets the first-stage PMOS sources from the averaged outputs. The error amplifier's current output into a diode, the bias with its resistor-set cascode drops, the Miller capacitor across the driver, the sizing and the targets are this library's, for SG13G2 at 1.2 V.