Designs › Fully differential › Instrumentation amplifiers
Capacitively coupled chopper IA, impedance boost
This sensor amplifier uses chopping to reduce low-frequency offset and noise. An extra feedback path supplies most of the charge drawn by its input capacitors, reducing the load on the sensor. Too much of this positive feedback can cause instability.
How it works
The capacitively coupled chopper amplifier with a positive-feedback loop that raises its input impedance. Everything else is the plain amplifier: an input chopper onto input capacitors, the chopper OTA, a feedback chopper onto the feedback capacitors that set the gain, and the servo capacitor that bounds the moved offset. A fourth chopper, in step with the input one, drives the output through CP1, CP2 onto the input side of the input capacitors, supplying most of the charge they draw at each edge, so the source supplies little.
As in the plain amplifier: the single-loop chopper OTA from Ib = 5 µA, outputs at vocm = 0.6 V, summing nodes held at vicm = 0.35 V by RB1, RB2, and one complementary 20 kHz clock pair for all five choppers - the positive-feedback one in step with the input one.
Signal path
- Input chopper (SI1n, SI1p, SI2n, SI2p, SI3n, SI3p, SI4n, SI4p): Transmission gates join inp to xp and inn to xn while clk is high, and cross them while clkb is: a DC input difference becomes a square wave at the chopping frequency.
- Input capacitors (CI1, CI2): CI1, CI2 (10 pF) pass the chopped difference to the summing nodes sp, sn and block the source's common mode: at every edge each draws a charge C_in·v_id.
- Summing nodes (RB1, RB2, M1, M2): sp and sn are the OTA's pair gates, held at vicm = 0.35 V by RB1, RB2 (5 MΩ); the loop keeps them a virtual ground, so the resistors carry almost no signal.
- OTA (M3, M5, M7, M9, SO1, SO2, SO3, SO4, M11, M13, CC1, RZ1, MC1, MC4): The single-loop chopper OTA: its output chopper SO1-SO4, in step with the input chopper, brings the signal back to baseband at g1, g2 and sends the first stage's offset and 1/f noise up to the chopping frequency.
- Feedback chopper and capacitors (SF1n, SF1p, SF2n, SF2p, SF3n, SF3p, SF4n, SF4p, CF1, CF2): The outputs are chopped again and returned crosswise through CF1, CF2 (0.5 pF): at each edge each feedback capacitor transfers charge C_fb·v_od, opposing the input charge C_in·v_id, so charge balance gives v_od/v_id ≈ C_in/C_fb. The narrow gates slow this charge to match the input's.
- Servo (CS1, CS2, SS1, SS2, SS3, SS4): CS1, CS2 (2 pF) from the outputs, chopped on their far side onto the summing nodes. For the steady signal they carry nothing; for a ripple at the chopping frequency, and for the OTA's offset across the summing nodes, they carry a charge at every edge - a resistor 1/(4 f_ch C_s) from the chopped output to the summing nodes that the signal cannot see.
- Positive-feedback loop (SP1n, SP1p, SP2n, SP2p, SP3n, SP3p, SP4n, SP4p, CP1, CP2): The outputs, chopped in step with the input, drive CP1, CP2 (0.475 pF) onto xp, xn: at each edge the input side of CI1, CI2 moves by the input difference while CP1, CP2's far side moves by G times it, so the loop delivers (G − 1)·C_pf of the charge.
Key relations
- Gain:
G = C_in/C_fb. 20 by the capacitors; 19.9 clocked at the defaults - the OTA's finite gain and the pair's gate capacitance take half a percent - and within about 1 % in every corner and draw. - Input impedance:
Z_in = 1/[2·f_ch·(C_in − (G − 1)·C_pf)]. (G − 1)·C_pf = 9 pF of the 10 pF: about 25 MΩ, against 2.5 MΩ without the loop; the clocked bench measures 24 MΩ. - Positive-feedback limit:
(G − 1)·C_pf < C_in. For a source too weak to supply any charge this ratio is a positive loop gain: 0.9 here, leaving room for the capacitors' mismatch and the switches' parasitics. - The moved offset:
D = (1 + R_sc/R_b)·V_os, R_sc = 1/(4·f_ch·C_s). The OTA's offset V_os leaves as a square wave of amplitude D at the output: R_sc = 6.25 MΩ against R_b = 5 MΩ holds it at 2.25·V_os - 9 mV peak to peak for the bench's 2 mV. - Without the servo:
dD/dt = V_os/(R_b·C_fb). The current the bias resistors draw from the offset would come off the feedback capacitors: 0.8 V/ms for 2 mV, to a rail within a millisecond.
Trade-offs
- Positive-feedback capacitor (Cpf): nearer C_in/(G − 1) boosts the impedance further, but the loop gain approaches one and the capacitors' mismatch can tip it into instability.
- Input capacitor (Cin): larger raises the gain for the same feedback capacitor and lowers the bias resistors' noise, but lowers the input impedance and takes area.
- Chopping frequency (fch): higher lowers the bias-resistor noise and the servo's resistance, but the input impedance falls with it, and every edge's spike comes more often.
- Servo capacitor (Cs): larger holds the moved offset closer to V_os and settles it in fewer edges, but loads the OTA's output; at 0 the ripple grows until the output hits a rail.
Testbenches and limits
- Operating point, clocks held: The amplifier with its clocks held in one phase - every chopper straight - and no input: the current it draws and the levels it sits at. Held, the loop has no path at DC but the bias resistors, so this is the operating point the clocked benches start from, not a figure of the running amplifier.
- Clocked: gain and input impedance: The choppers clocked, a DC difference on the inputs. The gain is the output difference averaged over whole clock periods, against the capacitor ratio that should set it; the input impedance is the input difference over the current the source delivers, averaged the same way - the charge the input capacitors draw at every edge.
- Clocked: the moved offset: The choppers clocked, no input, and a test source (Vos, 2 mV by default) in series with the gate of M1 inside the amplifier: an OTA offset of known size. Chopped, it should leave baseband and come out as a ripple at the chopping frequency; the bench reads what is left of it at baseband, how large the ripple is, and whether it grows - an offset held on the feedback capacitors that leaks away through the bias resistors grows without end.
| Bench | Figure | Limit |
|---|---|---|
| Operating point, clocks held | Supply current | ≤ 120 µA |
| Operating point, clocks held | Output common mode | ≥ 570 mV, ≤ 630 mV |
| Operating point, clocks held | Summing-node level | ≥ 330 mV, ≤ 370 mV |
| Clocked: gain and input impedance | Gain, clocked | ≥ 19.4 V/V, ≤ 20.6 V/V |
| Clocked: gain and input impedance | Gain against the capacitor ratio | ≥ -3 %, ≤ 3 % |
| Clocked: gain and input impedance | Input impedance, clocked | ≥ 12 MΩ |
| Clocked: gain and input impedance | Output excursion at the edges, peak to peak | ≤ 60 mV |
| Clocked: gain and input impedance | Output common mode | ≥ 570 mV, ≤ 630 mV |
| Clocked: the moved offset | Test offset left at baseband, input-referred | ≥ -40 µV, ≤ 40 µV |
| Clocked: the moved offset | Offset ripple, peak to peak | ≤ 35 mV |
| Clocked: the moved offset | Ripple growth | ≥ -2 V/s, ≤ 2 V/s |
Design variables and defaults
| Variable | Default |
|---|---|
| Input capacitor, each side | 10 pF |
| Feedback capacitor, each side | 500 fF |
| Servo capacitor, each side (0: none) | 2 pF |
| Summing-node bias resistor, each side | 5 MΩ |
| W input-chopper switch, NMOS half (PMOS twice) | 2 µm |
| W feedback-chopper switch, NMOS half (PMOS twice) | 300 nm |
| L input, feedback and servo switches | 130 nm |
| W servo-chopper switch | 1 µm |
| Positive-feedback capacitor, each side (0: no loop) | 475 fF |
| Reference current | 5 µA |
| W PMOS source unit (MB, MT, M13, M14) | 10 µm |
| L PMOS source unit | 2 µm |
| W NMOS unit (MB2, M3, M4, the CMFB tail) | 8 µm |
| L NMOS unit | 2 µm |
| W PMOS load unit (M7, M8 and the diode they copy) | 20 µm |
| L PMOS load unit | 2 µm |
| W input pair (M1, M2) | 20 µm |
| L input pair | 1 µm |
| W NMOS cascode (M5, M6) | 8 µm |
| L NMOS cascode | 500 nm |
| W PMOS cascode (M9, M10) | 6 µm |
| L PMOS cascode | 500 nm |
| W diode setting the NMOS cascode gate (MB6) | 1.6 µm |
| L diode setting the NMOS cascode gate | 4 µm |
| W diode setting the PMOS cascode gate (MB3) | 4 µm |
| L diode setting the PMOS cascode gate | 4 µm |
| W second-stage NMOS unit (M11, M12) | 800 nm |
| L second-stage NMOS unit | 2 µm |
| Second-stage current, in Ib | 4 |
| Miller capacitor, each side | 3 pF |
| Nulling resistor, each side | 12 kΩ |
| W output-chopper switch (SO1-SO4) | 1 µm |
| L output-chopper switch | 130 nm |
| W CMFB pair (MC1, MC2) | 10 µm |
| L CMFB pair | 1 µm |
| Common-mode sense resistor, each side | 1 MΩ |
| Common-mode sense capacitor, each side | 200 fF |
| Chopping frequency | 20 kHz |
| Input difference the clocked benches apply | 5 mV |
| Test offset the offset bench puts in the OTA | 2 mV |
| Input common mode, the source's | 600 mV |
| Summing-node level | 350 mV |
| Output common mode | 600 mV |
| Load capacitance, each output | 1 pF |
Ports
inpinputinninputoutpoutputoutnoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pinvocmbias: the output common modevicmbias: the summing nodes' level, the input pair's common modeclkclock: high: every chopper straightclkbclock: high: every chopper crossed
Reference
Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa, A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes, 2011. IEEE Journal of Solid-State Circuits, 46(7):1534-1543.
The capacitively coupled chopper amplifier and its positive-feedback loop that boosts the input impedance. Ours: the common-mode loop around both stages, the servo capacitor that bounds the moved offset, the loop's capacitor chosen for a positive-feedback gain of 0.9, and the sizing, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.