PMOS LDO, Miller-compensated with a zero resistor

How it works

A PMOS-pass LDO that needs no large output capacitor. The pass device MP is treated as the second stage of a two-stage amplifier and compensated across itself: Cc from its gate to its drain splits the poles, making the gate the dominant pole and leaving the output, g_m,MP over 100 pF, as the second. Rz in series with Cc moves the zero Cc would otherwise make in the right half-plane into the left. The rest - the five-transistor amplifier, MP and the divider - is the basic LDO's core: 0.9 V from 1.2 V at up to 5 mA.

Ib, 10 µA from outside, flows into the diode MB; the tail MT is N copies of it, 40 µA. The reference is an input, 0.6 V, and the supply is 1.2 V (1.08 to 1.32 V).

Signal path

• Feedback divider (R1, R2, R3): Three copies of one resistor, one above div and two below: div is two thirds of the output, and the loop holds it at V_ref. Their 30 µA are also the least MP ever carries.
• Error amplifier (M1, M2, M3, M4, MT): M1 takes div and M2 the reference, on the tail MT; the mirror M3, M4 turns M1's current round onto gate, so a rise in div lifts gate.
• Pass device (MP): A common-source PMOS from the input to the output: a higher gate means less current, so the output falls back.
• Miller compensation (Rz, Cc): Cc across MP multiplies into a large capacitance at gate: the dominant pole, and an angular crossover of about (2/3) · g_m2/Cc that hardly moves with the load. Rz in series turns the feed-forward zero from the right half-plane into the left.

Key relations

• Output voltage: V_out = 1.5 · V_ref. Three identical units in the divider.
• Crossover: f_c ≈ (2/3) · g_m2/(2π · Cc). Primarily set by amplifier transconductance and Cc; real parasitics and pass-device bias add load dependence.
• Output pole: f_2 ≈ g_m,MP/(2π · C_L). Lowest at no load, where MP carries only the divider's 30 µA: it must stay above twice f_c there.
• Zero: f_z = 1/(2π · Cc · (Rz − 1/g_m,MP)). In the left half-plane at every load once Rz is above 1/g_m,MP at no load, about 1.3 kΩ.

Trade-offs

• Cc: larger lowers the crossover and adds margin at no load, but the amplifier must slew a larger capacitance and the load step dips further.
• Rz: above 1/g_m,MP the zero adds phase; much larger and the loop gain flattens above the zero and the crossover wanders up with the load.
• Ru: the divider sets MP's current, and so its g_m, at no load - the output pole the whole compensation is sized against.
• CL: the design is rated for 100 pF; a larger load capacitance pulls the no-load output pole down and costs margin, 55° at 470 pF.

Testbenches and limits

• Operating point: The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.
• Load regulation: The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.
• Line regulation: The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.
• Dropout: The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.
• Loop gain: The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.
• Ringing across the loads: The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.
• Supply rejection: A ripple on the input, at the lightest and at the full load: how much of it reaches the output.
• Load step: The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.
• Line step: The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.
• Output noise: The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.

Design variables and defaults

Ports

• ref input: the reference voltage
• sense input: the output as the regulator reads it; the divider hangs from it
• out output
• vdd supply: the unregulated input
• vss ground
• ib bias: the bias current, driven into this pin

Reference

G. A. Rincon-Mora, Analog IC Design with Low-Dropout Regulators, 2nd, McGraw-Hill, 2014. the PMOS-pass LDO and its internal frequency compensation, for output capacitors too small to set the dominant pole.

The topology: a five-transistor error amplifier, a PMOS pass device and a feedback divider, compensated by a series R-C from the pass device's gate to the output. The sizing and specs are this library's, for SG13G2 at 1.2 V.

• B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2016