Basic PMOS LDO

How it works

The textbook low-dropout regulator. The PMOS pass device MP carries the load from the input to the output, and a five-transistor error amplifier sets its gate so that the divided output div equals the reference: V_out ≈ 1.5 V_ref, about 0.9 V. Nothing inside compensates the loop. The 1 µF output capacitor puts the dominant pole at the output, and the pass device's gate is the second pole, which the amplifier's output resistance must keep above the crossover at every load from none to 5 mA.

Ib, 10 µA from outside, flows into the diode MB; the tail MT is N copies of it, 40 µA. The reference is an input, 0.6 V, and the supply is 1.2 V (1.08 to 1.32 V).

Signal path

• Feedback divider (R1, R2, R3): Three copies of one resistor, one above div and two below: div is two thirds of the output, and the loop holds it at V_ref. Their 30 µA are also the least MP ever carries.
• Error amplifier (M1, M2, M3, M4, MT): M1 takes div and M2 the reference, on the tail MT; the mirror M3, M4 turns M1's current round onto gate, so a rise in div lifts gate.
• Pass device (MP): A common-source PMOS from the input to the output: a higher gate means less current, so the output falls back.
• Output capacitor and second pole (MP, M2, M4): The 1 µF on the output makes its pole the dominant one; gate, driven by the amplifier's output resistance through M2 and M4, carries MP's large gate capacitance and is the second pole.

Key relations

• Output voltage: V_out = V_ref · (R1 + R2 + R3)/(R2 + R3) = 1.5 · V_ref. The matched divider sets the ideal gain; amplifier offset, finite gain and mismatch leave error.
• Loop gain: T ≈ (2/3) · g_m2 · (r_o2 ∥ r_o4) · g_m,MP · R_o. R_o: MP's output resistance in parallel with the divider and the load; the loop gain is lowest at full load and the lowest input.
• Poles: f_out = 1/(2π · R_o · C_L); f_gate = 1/(2π · (r_o2 ∥ r_o4) · C_gate). The output pole moves over three decades with the load; f_gate must stay above the crossover, f_c ≈ (2/3) · A_EA · g_m,MP/(2π · C_L), which is highest at full load.
• Load regulation: ΔV_out ≈ n · V_T/((2/3) · A_EA) · ln(I_max/I_min). At light load MP is in weak inversion and its g_m follows its current, so the output falls logarithmically with the load range: most of it at light load.
• Dropout: V_DO ≈ I_L · R_on,MP. The amplifier cannot pull gate below its tail node plus M2's saturation voltage, about 0.4 V, so MP is sized for 5 mA with 0.68 V of V_SG.

Trade-offs

• Tail current (N): more of it lowers r_o2 ∥ r_o4 and lifts the gate pole; the amplifier's gain hardly changes, since in weak inversion it is V_A/(n · V_T) whatever the current.
• Wp and Lp (M3, M4): a wide, long mirror runs in weak inversion, so M4 stays saturated with gate close to V_DD at no load; much larger and the mirror's own pole at d1 comes down.
• Wpass and Lpass: a wider MP lowers the dropout but leaks more when hot and loads gate with more capacitance; a longer one halves the leakage for about a fifth more width.
• Ru: the divider is the bleed; a smaller unit holds the hot leakage down but adds V_out/(3 · Ru) to the quiescent current.
• CL: a larger output capacitor lowers the crossover and the undershoot and adds margin; a smaller one raises the crossover towards the gate pole.

Testbenches and limits

• Operating point: The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.
• Load regulation: The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.
• Line regulation: The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.
• Dropout: The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.
• Loop gain: The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.
• Ringing across the loads: The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.
• Supply rejection: A ripple on the input, at the lightest and at the full load: how much of it reaches the output.
• Load step: The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.
• Line step: The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.
• Output noise: The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.

Design variables and defaults

Ports

• ref input: the reference voltage
• sense input: the output as the regulator reads it; the divider hangs from it
• out output
• vdd supply: the unregulated input
• vss ground
• ib bias: the bias current, driven into this pin

Reference

G. A. Rincon-Mora, Analog IC Design with Low-Dropout Regulators, 2nd, McGraw-Hill, 2014. the PMOS-pass LDO: error amplifier, pass device and feedback divider, stabilized by the output capacitor's dominant pole.

The topology and the way it is stabilized: the output capacitor's pole dominant, the pass device's gate the second pole, which must stay above the crossover. The sizing, the unit-resistor divider and the specs are this library's, for SG13G2 at 1.2 V.