Designs › Digital › Digital logic
D flip-flop with reset
Capture one bit on a rising clock edge, with an active-low asynchronous reset.
How it works
The output remembers D at the rising edge. Reset asserts asynchronously, independently of a clock edge.
- Assert reset to establish a known state.
- Change D away from the active clock edge.
- Capture D and inspect the transistor-level clock-to-Q delay.
Design decisions and limits
- Reset release must respect recovery/removal in a real system, often using synchronized deassertion.
- These runs do not validate setup, hold, recovery, removal or metastability.
Try it
Explain why D changes between clock edges do not immediately change Q.
Interface
| Signal | Direction | Bits |
|---|---|---|
CLK | input | 1 |
D | input | 1 |
RESET_B | input | 1 |
Q | output | 1 |
What runs in the browser
Logic check · Cell transistors · Gate delays · SPICE · mapped cells · 25 expected-output checks · 1 IHP cells in the explicit example
IHP SG13G2 130 nm. Open the workspace to run its checks, synthesize it and simulate its delays in your browser.