Designs › Digital › Digital logic
2:1 multiplexer
Select one of two inputs; a basic element of datapaths and control logic.
How it works
S=0 selects A0; S=1 selects A1. A mux selects data, but its select input is itself a timing path.
- Test all eight input combinations.
- Use one IHP multiplexer cell.
- Compare data and select transitions in the live traces.
Design decisions and limits
- A select transition can glitch if data inputs also change; settled truth-table correctness is not glitch freedom.
- Transistor-level simulation models propagation and glitches; it is slower than event-driven gate simulation.
Try it
Hold A0=0 and A1=1. How does the output relate to S? Then swap A0 and A1.
Interface
| Signal | Direction | Bits |
|---|---|---|
A0 | input | 1 |
A1 | input | 1 |
S | input | 1 |
Y | output | 1 |
What runs in the browser
Logic check · Cell transistors · Gate delays · SPICE · mapped cells · 16 expected-output checks · 1 IHP cells in the explicit example
IHP SG13G2 130 nm. Open the workspace to run its checks, synthesize it and simulate its delays in your browser.