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Three-stage op amp, active-feedback compensation
This three-stage amplifier returns output changes through a capacitor and an active current buffer. That path stabilizes the amplifier while adding less unwanted delay near its operating bandwidth. The extra buffer improves the feedback response but consumes additional bias current.
How it works
A three-stage op amp whose outer compensation is an active feedback: a capacitor from the output into a common-gate buffer that drives the first stage's output. Below the buffer's corner it acts as a Miller capacitor; above it, as a conductance from the output back to o1, with a left-half-plane zero that lifts the phase near the crossover. An inner Miller capacitor wraps the output stage and the push-pull device feeds o1 forward.
The testbench draws Ib (2.5 µA) out of the diode MB. MT is two copies of it, so each input device carries Ib; M20 feeds Ib through Rb (116 kΩ) into the NMOS diode M21, so the cascode gate vbc sits Ib·Rb above vbn and the folding nodes rest near 0.3 V; the sinks M3/M4 are two copies of M21 each, leaving Ib for each cascode. M12 is one copy of MB, so the second stage runs at Ib, and M14 is sixteen copies of M9 on the same gate: the output stage carries about 40 µA nominally; drain-voltage differences and mismatch cause deviations from the ideal copy ratio. The buffer runs at 2·Ib: M16 is two copies of M21, M3 has two copies more than M4 so the mirror carries the buffer's bias into o1, and M7/M8 are sized for the three units of current they carry.
Signal path
- First stage (M1, M2, MT, M3, M4, M5, M6, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises.
- Second stage (M9, M10, M11, M12): M9 turns o1 into a current, the NMOS mirror M10/M11 copies it onto o2 against the source M12: a non-inverting stage, o2 rises with o1. It runs at one Ib, slow on purpose.
- Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
- Active feedback (Ca, M15, M16, M23): Ca couples out into a, the source of the common-gate M15 on vbc, which passes the current into o1; M16 sinks the buffer's bias, and the first stage's mirror supplies it into o1, with M23 beside M5 keeping the cascodes at M15's density.
- Inner Miller capacitor (Cm): Cm from out to o2 wraps the inverting output stage and splits the o2 and output poles.
Key relations
- DC gain:
A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long. - Unity-gain frequency:
ω_u ≈ g_m1/C_a. About 4.6 MHz with Ca at 2 pF. - Buffer zero:
ω_z ≈ g_m15/C_a. Where the feedback turns from capacitive to resistive; it sits near ω_u, so the phase margin is near 100°. - Flat gain above the buffer's corner:
|A| → g_m1/g_m15. Only well below 0 dB if the buffer is faster than the input pair: hence two Ib in M15 against one in each input device.
Trade-offs
- Ka: more buffer current raises g_m15 and the gain margin, but its bias flows through o1's mirror and lowers the DC gain.
- Ca: larger lowers ω_u and moves the buffer's zero down, pushing the phase margin further past 90°.
- Cm: larger raises the gain margin; smaller speeds the pole pair.
- With the buffer as slow as the input pair (Ka = 1) the gain sits near 0 dB over a decade and the loop rings.
Testbenches and limits
- Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
- Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
- Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
- Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
- Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
- Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
| Bench | Figure | Limit |
|---|---|---|
| Operating point | Supply current | ≤ 85 µA |
| Open-loop gain | DC open-loop gain | ≥ 88 dB |
| Open-loop gain | Unity-gain frequency | ≥ 2 MHz |
| Open-loop gain | Phase margin | ≥ 60 deg |
| Open-loop gain | Gain margin | ≥ 10 dB |
| Step response | Settling time, 1 % | ≤ 800 ns |
| Step response | Overshoot | ≤ 5 % |
| Supply rejection | Supply rejection at 1 kHz | ≥ 60 dB |
| Common-mode rejection | Common-mode rejection at 1 kHz | ≥ 75 dB |
Design variables and defaults
| Variable | Default |
|---|---|
| Reference current | 2.5 µA |
| W PMOS source unit (MB and its copies) | 5.4 µm |
| L PMOS source unit | 2 µm |
| W input pair (M1, M2) | 17.9 µm |
| L input pair | 1 µm |
| W NMOS sink unit (M21 and its copies) | 1.4 µm |
| L NMOS sink unit | 2 µm |
| Cascode bias resistor | 116 kΩ |
| W cascode unit (M5, M6) | 3.2 µm |
| L cascode unit | 1 µm |
| W mirror load (M7, M8) | 24.2 µm |
| L mirror load | 3 µm |
| W second-stage PMOS unit (M9, M14) | 2.5 µm |
| L second-stage PMOS unit | 500 nm |
| W second-stage mirror (M10, M11) | 5.4 µm |
| L second-stage mirror | 4 µm |
| W output NMOS unit (M13) | 5.7 µm |
| L output NMOS unit | 2 µm |
| Tail current, in Ib | 2 |
| Folding-sink current, in Ib | 2 |
| Second-stage current, in unit copies | 1 |
| Output-stage current, in second-stage currents | 16 |
| Output NMOS copies | 4 |
| Inner Miller capacitor | 1 pF |
| Active-feedback capacitor | 2 pF |
| Buffer current, in Ib | 2 |
| Load capacitance | 10 pF |
| Input common mode | 400 mV |
Ports
inpinputinninputoutoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pin
Reference
H. Lee, P. K. T. Mok, Active-feedback frequency-compensation technique for low-power multistage amplifiers, 2003. IEEE Journal of Solid-State Circuits, 38(3):511-520.
The active-feedback frequency compensation (AFFC): the outer feedback through a capacitor in series with a positive-gain (common-gate) stage into the first stage's output, an inner Miller capacitor around the output stage, and a feedforward output device. The core amplifier, its bias, the buffer's biasing by unit copies and every size are this library's, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.