Three-stage op amp, active-zero compensation

How it works

A three-stage op amp compensated by one Miller capacitor returned through the first stage's regulated cascode - a fast current buffer, with no feedforward of its own - and a second-stage mirror whose diode is gated through a resistor: an active zero that cancels the mirror's own pole. The push-pull device feeds o1 forward to the output.

The testbench draws Ib (2.5 µA) out of MB. MT is one copy, each input device carries half an Ib, and the sinks, two copies of M21, leave 1.5 Ib for each cascode. The regulators MA1, MA2 are copies of M21 at Ib each, fed by MR (two copies of MB) through Rr1, Rr2 (80 kΩ): the folding nodes rest at M21's V_GS. M12 sets the second stage at Ib and M14, sixteen copies of M9, gives the output 40 µA. The PMOS source and NMOS sink units are 4 µm long at the same current densities as before, four times the original area, to reduce their mismatch contribution.

Signal path

• First stage (M1, M2, MT, M3, M4, M5, M6, MA1, MA2, Rr1, Rr2, MR, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6. Each cascode's gate is driven by a regulator, MA1 or MA2, off its own source and loaded by Rr1 or Rr2 from the source MR, so the folding nodes f1, f2 are held at the regulators' V_GS and look into a resistance several times lower. The mirror M7/M8 gives the output o1.
• Second stage, active zero (M9, M10, Rz2, M11, M12): M9 turns o1 into a current into the diode M10, whose gate is taken from d2 through Rz2; M11 mirrors it onto o2 against the source M12. The diode's impedance rises with frequency, so the mirror's gain gains a zero.
• Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
• Miller capacitor (Cm, M6): Cm injects the output's current into f2, the regulated cascode M6's source, which carries it to o1 and sets the dominant pole.

Key relations

• DC gain: A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long.
• Unity-gain frequency: ω_u ≈ g_m1/C_m. About 2.7 MHz with Cm at 1.6 pF.
• Buffer resistance: r_x ≈ 1/(g_m6 (1 + g_m,MA2 R_r)). Local regulation lowers the resistance seen at the cascode source, making the compensation-current buffer faster. Its improvement depends on the regulator transconductance and load at the operating point.
• Active zero: i_M11/i_M9 ≈ (1 + s R_z2 C_gs10)/(1 + s C_d2/g_m10 + s^2 R_z2 C_gs10 C_d2/g_m10). ζ ≈ 0.5 √(C_d2/(g_m10 R_z2 C_gs10)): with g_m10·Rz2 near 0.75 the mirror is just damped; much larger and it rings.

Trade-offs

• Rz2: about 20 kΩ adds a little gain margin; above about 100 kΩ the diode becomes an active inductor and the step oscillates.
• Rr: larger raises the regulator's gain but takes MR out of saturation at the slow, low-supply corner.
• Cm: larger lowers ω_u and raises the gain margin.
• The regulated cascode gives back most of the gain the fast-cascode current ratio costs: about 100 dB at tt.
• Source and sink unit area: 4 µm lengths suppress random common-mode conversion; still larger units add capacitance to the regulated folding nodes and erode the local-loop margin.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin

Reference

W. Qu, S. Singh, Y. Lee, Y.-S. Son, G.-H. Cho, Design-Oriented Analysis for Miller Compensation and Its Application to Multistage Amplifier Design, 2017. IEEE Journal of Solid-State Circuits, 52(2):517-527.

Miller compensation returned through a regulated-cascode current buffer, an active zero in the second stage made by gating a mirror diode through a resistor, and a feedforward output device. The core amplifier, its bias and every size are this library's, for SG13G2 at 1.2 V.