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Three-stage op amp, cross feedforward cascode
This three-stage amplifier returns compensation current through its first-stage cascode. Two direct signal paths help drive the later stages before the slower main path responds. The arrangement supports high gain with one compensation capacitor, but depends on carefully balanced internal speeds.
How it works
A three-stage op amp with one capacitor, returned to the first stage through its cascode, and two feedforward paths: the output device driven from the first stage's output, and the second stage's load driven from the first stage's mirror node, which moves opposite to o1. The second stage is slow on purpose, so near the unity-gain frequency the feedforward carries the loop the capacitor closes.
The testbench draws Ib (2.5 µA) out of MB. MT is one copy, so each input device carries half an Ib; the sinks are two copies of M21, leaving 1.5 Ib, 3.75 µA, for each cascode; Rb lifts the cascode gate above vbn. M7/M8 are four units each, and M12 one unit on x1, so the second stage runs at 0.94 µA; M14, thirty-two copies of M9, gives the output 30 µA. The input pair is 2 µm long, the PMOS source unit 6 µm and the NMOS sink unit 8 µm, keeping the same current densities with more matching area.
Signal path
- First stage (M1, M2, MT, M3, M4, M5, M6, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises.
- Second stage (M9, M10, M11, M12): M9 into the mirror M10/M11: at the default K2 = 1 and Km = 4, stage 2 carries one unit of current, one quarter of the full four-unit mirror branch. It is a slow non-inverting stage onto o2.
- Cross feedforward (M12, M7): M12, the load of o2, is one of the four units the mirror M7/M8 is built from, gated by x1: it adds the first stage's signal to o2 in phase with M11's.
- Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, thirty-two copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
- Cascode compensation (Cm, M6): Cm injects the output's current into f2, the source of the cascode M6, which carries it to o1 and sets the dominant pole.
Key relations
- DC gain:
A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long. - Unity-gain frequency:
ω_u ≈ g_m1/C_m. About 3.9 MHz with Cm at 1.3 pF. - Current buffer:
g_m6 ≈ 3 g_m1. The pair runs at one Ib against three in each cascode: above g_m6/C_m the cascode passes a conductance, not a capacitive current, and together with the feedforward M14 that loop stays damped only while the cascode is several times faster than the input pair. - Local loop through Cm:
T_i ≈ (C_m/C_o1) g_m14/(s C_L). Near ω_u the feedforward M14 carries it; a fast second stage would add phase and make it ring.
Trade-offs
- Cm: larger lowers ω_u and raises the phase margin; smaller, the loop through the cascode peaks.
- The second stage's current (Km, K2): more of it speeds the second stage and the local loop loses margin.
- Kt and Ks: a faster input pair relative to the cascodes raises the gain but takes the gain margin to a few dB.
- M13's gate keeps o2 slow; a smaller output device costs gain margin.
- First-stage matching area: the 2/6/8 µm input/source/sink lengths keep all forty common-mode-rejection draws above 90 dB; their added capacitance is bounded by the cascode-current ratio and was checked in the step response.
Testbenches and limits
- Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
- Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
- Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
- Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
- Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
- Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
| Bench | Figure | Limit |
|---|---|---|
| Operating point | Supply current | ≤ 60 µA |
| Open-loop gain | DC open-loop gain | ≥ 92 dB |
| Open-loop gain | Unity-gain frequency | ≥ 2 MHz |
| Open-loop gain | Phase margin | ≥ 60 deg |
| Open-loop gain | Gain margin | ≥ 6 dB |
| Step response | Settling time, 1 % | ≤ 800 ns |
| Step response | Overshoot | ≤ 5 % |
| Supply rejection | Supply rejection at 1 kHz | ≥ 70 dB |
| Common-mode rejection | Common-mode rejection at 1 kHz | ≥ 90 dB |
Design variables and defaults
| Variable | Default |
|---|---|
| Reference current | 2.5 µA |
| W PMOS source unit (MB and its copies) | 16.1 µm |
| L PMOS source unit | 6 µm |
| W input pair (M1, M2) | 17.9 µm |
| L input pair | 2 µm |
| W NMOS sink unit (M21 and its copies) | 5.7 µm |
| L NMOS sink unit | 8 µm |
| Cascode bias resistor | 116 kΩ |
| W cascode unit (M5, M6) | 4.9 µm |
| L cascode unit | 1 µm |
| W mirror-load unit (M7, M8, M12) | 3 µm |
| L mirror-load unit | 3 µm |
| Mirror-load copies (M7, M8) | 4 |
| W second-stage PMOS unit (M9, M14) | 1.9 µm |
| L second-stage PMOS unit | 1 µm |
| W second-stage mirror (M10, M11) | 2 µm |
| L second-stage mirror | 4 µm |
| W output NMOS unit (M13) | 8.6 µm |
| L output NMOS unit | 4 µm |
| Tail current, in Ib | 1 |
| Folding-sink current, in Ib | 2 |
| Second-stage current, in unit copies | 1 |
| Output-stage current, in second-stage currents | 32 |
| Output NMOS copies | 4 |
| Compensation capacitor (to f2) | 1.3 pF |
| Load capacitance | 10 pF |
| Input common mode | 400 mV |
Ports
inpinputinninputoutoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pin
Reference
S. S. Chong, P. K. Chan, Cross Feedforward Cascode Compensation for Low-Power Three-Stage Amplifier With Large Capacitive Load, 2012. IEEE Journal of Solid-State Circuits, 47(9):2227-2234.
The cross feedforward cascode compensation (CFCC): one capacitor returned through the first-stage cascode, a feedforward output device on the first stage's output, and a second-stage load driven from the first stage's mirror node, with the second stage kept slow. The core amplifier, its bias, the current ratios the cascode return needs and every size are this library's, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.