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Three-stage op amp, damping-factor control, stage 2
This three-stage amplifier adds a small damping circuit to the second-stage output. The circuit acts mainly at higher frequencies, where it helps suppress ringing without reducing the main DC gain. Better settling comes at the cost of extra devices and current.
How it works
A three-stage op amp with one Miller capacitor and a damping-factor-control block on the second stage's output: a small gain stage wrapped in a capacitor. Seen from o2 it is a capacitance at low frequency and a conductance of about its own g_m above its corner, so it loads o2 only where the non-dominant poles are and damps them there, without touching the DC gain.
The testbench draws Ib (2.5 µA) out of the diode MB. MT is two copies of it, so each input device carries Ib; M20 feeds Ib through Rb (116 kΩ) into the NMOS diode M21, so the cascode gate vbc sits Ib·Rb above vbn and the folding nodes rest near 0.3 V; the sinks M3/M4 are two copies of M21 each, leaving Ib for each cascode. M12 is one copy of MB, so the second stage runs at Ib, and M14 is sixteen copies of M9 on the same gate: the output stage carries about 40 µA nominally; drain-voltage differences and mismatch cause deviations from the ideal copy ratio. M15 shares o2 with M13 and so carries a quarter of the output current, 10 µA; M16, four copies of MB, nominally supplies the same current, keeping d near mid-supply; drain-voltage differences and mismatch leave residual imbalance.
Signal path
- First stage (M1, M2, MT, M3, M4, M5, M6, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises.
- Second stage (M9, M10, M11, M12): M9 turns o1 into a current, the NMOS mirror M10/M11 copies it onto o2 against the source M12: a non-inverting stage, o2 rises with o1. It runs at one Ib, slow on purpose.
- Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
- DFC block (M15, M16, Cd): M15, a copy of the output device's unit on o2, inverts o2 onto d against the source M16; Cd wraps it from d back to o2.
- Miller capacitor (Cm): Cm from out to o1 sets the dominant pole.
Key relations
- DC gain:
A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long. - Unity-gain frequency:
ω_u ≈ g_m1/C_m. About 2.6 MHz with Cm at 3 pF. - DFC block:
Y_d ≈ s C_d (1 + g_m15 R_d)/(1 + s C_d R_d). R_d is the resistance at d; capacitive below 1/(R_d C_d), a conductance near g_m15 above. - Balance:
M16 = M_d K_f K_2/N_3 copies of MB. Or d runs to a rail and the block loses its gain.
Trade-offs
- Cd: above about 1 pF its value barely matters - the block is already a conductance at the crossover; without it the gain margin falls from 16 dB to about 5.
- Md: more copies raise g_m15 and the damping, at the cost of current.
- Cm: larger lowers ω_u and raises the phase margin.
- Any change to Kf, K2 or N3 must keep M16's count equal to M15's current, or d leaves the middle of the supply.
Testbenches and limits
- Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
- Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
- Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
- Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
- Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
- Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
| Bench | Figure | Limit |
|---|---|---|
| Operating point | Supply current | ≤ 85 µA |
| Open-loop gain | DC open-loop gain | ≥ 100 dB |
| Open-loop gain | Unity-gain frequency | ≥ 1.5 MHz |
| Open-loop gain | Phase margin | ≥ 60 deg |
| Open-loop gain | Gain margin | ≥ 10 dB |
| Step response | Settling time, 1 % | ≤ 800 ns |
| Step response | Overshoot | ≤ 5 % |
| Supply rejection | Supply rejection at 1 kHz | ≥ 60 dB |
| Common-mode rejection | Common-mode rejection at 1 kHz | ≥ 80 dB |
Design variables and defaults
| Variable | Default |
|---|---|
| Reference current | 2.5 µA |
| W PMOS source unit (MB and its copies) | 5.4 µm |
| L PMOS source unit | 2 µm |
| W input pair (M1, M2) | 17.9 µm |
| L input pair | 1 µm |
| W NMOS sink unit (M21 and its copies) | 1.4 µm |
| L NMOS sink unit | 2 µm |
| Cascode bias resistor | 116 kΩ |
| W cascode unit (M5, M6) | 3.2 µm |
| L cascode unit | 1 µm |
| W mirror load (M7, M8) | 8.1 µm |
| L mirror load | 3 µm |
| W second-stage PMOS unit (M9, M14) | 2.5 µm |
| L second-stage PMOS unit | 500 nm |
| W second-stage mirror (M10, M11) | 5.4 µm |
| L second-stage mirror | 4 µm |
| W output NMOS unit (M13) | 5.7 µm |
| L output NMOS unit | 2 µm |
| Tail current, in Ib | 2 |
| Folding-sink current, in Ib | 2 |
| Second-stage current, in unit copies | 1 |
| Output-stage current, in second-stage currents | 16 |
| Output NMOS copies | 4 |
| Miller capacitor | 3 pF |
| DFC capacitor | 1 pF |
| DFC stage copies of the M13 unit | 1 |
| Load capacitance | 10 pF |
| Input common mode | 400 mV |
Ports
inpinputinninputoutoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pin
Reference
K. N. Leung, P. K. T. Mok, Analysis of multistage amplifier-frequency compensation, 2001. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 48(9):1041-1056.
Damping-factor-control frequency compensation (DFCFC) with the DFC block - a gain stage wrapped in a capacitor - at the second stage's output, one Miller capacitor to the first stage's output and a feedforward output device. The core amplifier, its bias, the DFC stage's biasing by unit copies and every size are this library's, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.