Designs › Op amps and OTAs › Three-stage op amps
Three-stage op amp, nested Miller with feedforward
This amplifier connects three gain stages and stabilizes them with two nested compensation capacitors. A direct path from the first stage to the output helps damp the faster internal response. The capacitors and output current set the tradeoff between speed and stability.
How it works
A three-stage op amp for about 100 dB of gain into a capacitive load, made stable by nested Miller compensation with a feedforward output. Three gain stages give three low-frequency poles; Cm1 from the output to the first stage's output makes that node the dominant pole, Cm2 around the output stage splits the other two, and the push-pull device M14, driven from o1, feeds the signal forward: it damps the non-dominant pole pair and turns nested Miller's lower zero left-half-plane.
The testbench draws Ib (2.5 µA) out of the diode MB. MT is two copies of it, so each input device carries Ib; M20 feeds Ib through Rb (116 kΩ) into the NMOS diode M21, so the cascode gate vbc sits Ib·Rb above vbn and the folding nodes rest near 0.3 V; the sinks M3/M4 are two copies of M21 each, leaving Ib for each cascode. M12 is one copy of MB, so the second stage runs at Ib, and M14 is sixteen copies of M9 on the same gate: the output stage carries about 40 µA nominally; drain-voltage differences and mismatch cause deviations from the ideal copy ratio.
Signal path
- First stage (M1, M2, MT, M3, M4, M5, M6, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises.
- Second stage (M9, M10, M11, M12): M9 turns o1 into a current, the NMOS mirror M10/M11 copies it onto o2 against the source M12: a non-inverting stage, o2 rises with o1. It runs at one Ib, slow on purpose.
- Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
- Nested Miller capacitors (Cm1, Cm2): Cm1 from out to o1, multiplied by the gain of the last two stages, sets the dominant pole; Cm2 from out to o2 wraps the inverting output stage and splits the o2 and output poles.
Key relations
- DC gain:
A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long. - Unity-gain frequency:
ω_u ≈ g_m1/C_m1. About 2.7 MHz with Cm1 at 3.2 pF. - Non-dominant poles:
1 + s C_m2 (g_m13 + g_m14 − g_m9)/(g_m9 g_m13) + s^2 C_m2 C_L/(g_m9 g_m13). ω_n ≈ √(g_m9 g_m13/(C_m2 C_L)); the feedforward g_m14 adds to the damping term. - Zeros:
1 + s C_m2 (g_m14 − g_m9)/(g_m9 g_m13) − s^2 C_m1 C_m2/(g_m9 g_m13). With g_m14 above g_m9 the lower zero is in the left half-plane.
Trade-offs
- Cm1: larger lowers ω_u and raises the phase margin; below about 2.5 pF the fast, cold corner falls under 60°.
- Cm2: larger lowers the pole pair's ω_n and the phase margin but raises the gain margin; smaller does the reverse.
- Kf: more output current raises g_m13 and g_m14, pushing the pole pair out, at the cost of supply current.
- Ib: every current scales with it, and ω_u with the input pair's g_m; the gain barely moves.
Testbenches and limits
- Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
- Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
- Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
- Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
- Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
- Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
| Bench | Figure | Limit |
|---|---|---|
| Operating point | Supply current | ≤ 75 µA |
| Open-loop gain | DC open-loop gain | ≥ 100 dB |
| Open-loop gain | Unity-gain frequency | ≥ 1.5 MHz |
| Open-loop gain | Phase margin | ≥ 60 deg |
| Open-loop gain | Gain margin | ≥ 8 dB |
| Step response | Settling time, 1 % | ≤ 800 ns |
| Step response | Overshoot | ≤ 5 % |
| Supply rejection | Supply rejection at 1 kHz | ≥ 60 dB |
| Common-mode rejection | Common-mode rejection at 1 kHz | ≥ 80 dB |
Design variables and defaults
| Variable | Default |
|---|---|
| Reference current | 2.5 µA |
| W PMOS source unit (MB and its copies) | 5.4 µm |
| L PMOS source unit | 2 µm |
| W input pair (M1, M2) | 17.9 µm |
| L input pair | 1 µm |
| W NMOS sink unit (M21 and its copies) | 1.4 µm |
| L NMOS sink unit | 2 µm |
| Cascode bias resistor | 116 kΩ |
| W cascode unit (M5, M6) | 3.2 µm |
| L cascode unit | 1 µm |
| W mirror load (M7, M8) | 8.1 µm |
| L mirror load | 3 µm |
| W second-stage PMOS unit (M9, M14) | 2.5 µm |
| L second-stage PMOS unit | 500 nm |
| W second-stage mirror (M10, M11) | 5.4 µm |
| L second-stage mirror | 4 µm |
| W output NMOS unit (M13) | 5.7 µm |
| L output NMOS unit | 2 µm |
| Tail current, in Ib | 2 |
| Folding-sink current, in Ib | 2 |
| Second-stage current, in unit copies | 1 |
| Output-stage current, in second-stage currents | 16 |
| Output NMOS copies | 4 |
| Outer Miller capacitor | 3.2 pF |
| Inner Miller capacitor | 400 fF |
| Load capacitance | 10 pF |
| Input common mode | 400 mV |
Ports
inpinputinninputoutoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pin
Reference
K. N. Leung, P. K. T. Mok, Analysis of multistage amplifier-frequency compensation, 2001. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 48(9):1041-1056.
The nested Miller compensation with a feedforward transconductance (NMCF): Cm1 from the output to the first stage's output, Cm2 from the output to the second stage's output, and a feedforward stage from the first stage's output to the output, with the paper's conditions on the feedforward. The core amplifier, its bias and every size are this library's, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.