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Three-stage op amp, single Miller capacitor
This three-stage amplifier uses just one main compensation capacitor. A direct signal path to the output helps damp the response, while the second stage is deliberately kept slow. Fewer compensation capacitors save area, but the internal speeds must be carefully balanced.
How it works
A three-stage op amp compensated by one Miller capacitor alone, from the output to the first stage's output, with no capacitor on the second stage's output. The o2 and output poles then form a pair damped only by the feedforward output device and by how slow the second stage is: its g_m over o2's capacitance must stay below about half of the output stage's over the load, so the second stage runs at one Ib and the output device's gate loads o2.
The testbench draws Ib (2.5 µA) out of the diode MB. MT is two copies of it, so each input device carries Ib; M20 feeds Ib through Rb (116 kΩ) into the NMOS diode M21, so the cascode gate vbc sits Ib·Rb above vbn and the folding nodes rest near 0.3 V; the sinks M3/M4 are two copies of M21 each, leaving Ib for each cascode. M12 is one copy of MB, so the second stage runs at Ib, and M14 is sixteen copies of M9 on the same gate: the output stage carries about 40 µA nominally; drain-voltage differences and mismatch cause deviations from the ideal copy ratio. M13 is long (4 µm) so its gate adds capacitance to o2.
Signal path
- First stage (M1, M2, MT, M3, M4, M5, M6, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises.
- Second stage (M9, M10, M11, M12): M9 turns o1 into a current, the NMOS mirror M10/M11 copies it onto o2 against the source M12: a non-inverting stage, o2 rises with o1. It runs at one Ib, slow on purpose.
- Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
- Miller capacitor (Cm): The single capacitor Cm from out to o1, multiplied by the gain of the last two stages, sets the dominant pole; o2 carries only M13's gate.
Key relations
- DC gain:
A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long. - Unity-gain frequency:
ω_u ≈ g_m1/C_m. About 2.8 MHz with Cm at 3.5 pF. - Non-dominant pair:
ω_n ≈ √(g_m9 g_m13/(C_o2 C_L')). C_L' = C_L + C_o1 (1 + C_L/C_m) counts o1's own capacitance. - Damping:
ζ ≈ (g_m14/2) √(C_o2/(g_m9 g_m13 C_L')). Set by the feedforward and by a slow second stage: g_m9/C_o2 below half of g_m13/C_L.
Trade-offs
- Cm: larger lowers ω_u and raises the phase margin; below about 3 pF the fast corners fall under 60°.
- The second stage's current: more of it raises g_m9, the pair loses its damping and the gain margin falls towards 0 dB.
- M13's size: a smaller gate speeds o2 and costs gain margin, which is why the output device is longer than the other stages'.
- Kf: more output current raises g_m14 and the damping, at the cost of supply current.
Testbenches and limits
- Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
- Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
- Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
- Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
- Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
- Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
| Bench | Figure | Limit |
|---|---|---|
| Operating point | Supply current | ≤ 75 µA |
| Open-loop gain | DC open-loop gain | ≥ 100 dB |
| Open-loop gain | Unity-gain frequency | ≥ 1.5 MHz |
| Open-loop gain | Phase margin | ≥ 60 deg |
| Open-loop gain | Gain margin | ≥ 8 dB |
| Step response | Settling time, 1 % | ≤ 800 ns |
| Step response | Overshoot | ≤ 5 % |
| Supply rejection | Supply rejection at 1 kHz | ≥ 60 dB |
| Common-mode rejection | Common-mode rejection at 1 kHz | ≥ 80 dB |
Design variables and defaults
| Variable | Default |
|---|---|
| Reference current | 2.5 µA |
| W PMOS source unit (MB and its copies) | 5.4 µm |
| L PMOS source unit | 2 µm |
| W input pair (M1, M2) | 17.9 µm |
| L input pair | 1 µm |
| W NMOS sink unit (M21 and its copies) | 1.4 µm |
| L NMOS sink unit | 2 µm |
| Cascode bias resistor | 116 kΩ |
| W cascode unit (M5, M6) | 3.2 µm |
| L cascode unit | 1 µm |
| W mirror load (M7, M8) | 8.1 µm |
| L mirror load | 3 µm |
| W second-stage PMOS unit (M9, M14) | 2.5 µm |
| L second-stage PMOS unit | 500 nm |
| W second-stage mirror (M10, M11) | 5.4 µm |
| L second-stage mirror | 4 µm |
| W output NMOS unit (M13) | 11.4 µm |
| L output NMOS unit | 4 µm |
| Tail current, in Ib | 2 |
| Folding-sink current, in Ib | 2 |
| Second-stage current, in unit copies | 1 |
| Output-stage current, in second-stage currents | 16 |
| Output NMOS copies | 4 |
| Miller capacitor | 3.5 pF |
| Load capacitance | 10 pF |
| Input common mode | 400 mV |
Ports
inpinputinninputoutoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pin
Reference
X. Fan, C. Mishra, E. Sanchez-Sinencio, Single Miller capacitor frequency compensation technique for low-power multistage amplifiers, 2005. IEEE Journal of Solid-State Circuits, 40(3):584-592.
The single Miller capacitor compensation (SMC): one capacitor from the output to the first stage's output, none on the second stage's output, and a feedforward transconductance from the first stage's output to the output that damps the non-dominant pole pair. The core amplifier, its bias, the slow second stage and every size are this library's, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.