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Three-stage op amp, buffered capacitance feedback
This three-stage amplifier sends one compensation current through a buffer before it reaches the second stage. The buffer helps control the faster internal response, while another capacitor sets the main bandwidth. The buffer must remain fast enough to avoid adding unwanted delay.
How it works
A three-stage op amp with an outer Miller capacitor and a second capacitor returned from the output to the second stage's output through a current buffer. The buffer's transconductance adds to the second stage's at high frequency, raising the non-dominant poles, and the capacitor-buffer pair adds a left-half-plane zero; the buffer must stay fast, or its own node puts a pole inside the loop.
The testbench draws Ib (2.5 µA) out of the diode MB. MT is two copies of it, so each input device carries Ib; M20 feeds Ib through Rb (116 kΩ) into the NMOS diode M21, so the cascode gate vbc sits Ib·Rb above vbn and the folding nodes rest near 0.3 V; the sinks M3/M4 are two copies of M21 each, leaving Ib for each cascode. M12 is one copy of MB, so the second stage runs at Ib, and M14 is sixteen copies of M9 on the same gate: the output stage carries about 40 µA nominally; drain-voltage differences and mismatch cause deviations from the ideal copy ratio. M15, two copies of M9, carries the second stage's Ib; with its gate on vbn, t rests one V_SG above an NMOS V_GS, near 0.8 V, which keeps M12 and M15 saturated.
Signal path
- First stage (M1, M2, MT, M3, M4, M5, M6, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises.
- Second stage (M9, M10, M11, M12, M15): M9 turns o1 into a current mirrored by M10/M11 onto o2; the source M12 feeds o2 through the common-gate buffer M15, whose gate sits on vbn.
- Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
- Capacitance feedback (Ca, M15): Ca couples out into t, M15's source, which passes the current into o2: Miller feedback around the output stage through a current buffer.
- Outer Miller capacitor (Cm): Cm from out to o1 sets the dominant pole.
Key relations
- DC gain:
A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long. - Unity-gain frequency:
ω_u ≈ g_m1/C_m. About 2.7 MHz with Cm at 3 pF. - Non-dominant poles:
ω_n ≈ √((g_m9 + g_m15) g_m13/(C_o2 C_L)). The buffer's g_m adds to the second stage's above its corner. - Left-half-plane zero:
ω_z ≈ g_m15/C_a. Comes with a real pole near g_m9 g_m15/((g_m9 + g_m15) C_a).
Trade-offs
- Ca: small is best; larger moves the buffer's zero and pole down and the step overshoots more.
- M15: short and fast; a long buffer slows t and the capacitance-feedback loop rings.
- Cm: larger lowers ω_u and raises the phase margin.
- Ib: scales every current and ω_u.
Testbenches and limits
- Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
- Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
- Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
- Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
- Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
- Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
| Bench | Figure | Limit |
|---|---|---|
| Operating point | Supply current | ≤ 75 µA |
| Open-loop gain | DC open-loop gain | ≥ 100 dB |
| Open-loop gain | Unity-gain frequency | ≥ 1.5 MHz |
| Open-loop gain | Phase margin | ≥ 60 deg |
| Open-loop gain | Gain margin | ≥ 10 dB |
| Step response | Settling time, 1 % | ≤ 800 ns |
| Step response | Overshoot | ≤ 5 % |
| Supply rejection | Supply rejection at 1 kHz | ≥ 60 dB |
| Common-mode rejection | Common-mode rejection at 1 kHz | ≥ 80 dB |
Design variables and defaults
| Variable | Default |
|---|---|
| Reference current | 2.5 µA |
| W PMOS source unit (MB and its copies) | 5.4 µm |
| L PMOS source unit | 2 µm |
| W input pair (M1, M2) | 17.9 µm |
| L input pair | 1 µm |
| W NMOS sink unit (M21 and its copies) | 1.4 µm |
| L NMOS sink unit | 2 µm |
| Cascode bias resistor | 116 kΩ |
| W cascode unit (M5, M6) | 3.2 µm |
| L cascode unit | 1 µm |
| W mirror load (M7, M8) | 8.1 µm |
| L mirror load | 3 µm |
| W second-stage PMOS unit (M9, M14) | 2.5 µm |
| L second-stage PMOS unit | 500 nm |
| W second-stage mirror (M10, M11) | 5.4 µm |
| L second-stage mirror | 4 µm |
| W output NMOS unit (M13) | 5.7 µm |
| L output NMOS unit | 2 µm |
| Tail current, in Ib | 2 |
| Folding-sink current, in Ib | 2 |
| Second-stage current, in unit copies | 1 |
| Output-stage current, in second-stage currents | 16 |
| Output NMOS copies | 4 |
| Miller capacitor | 3 pF |
| Feedback capacitor (into the buffer) | 500 fF |
| Load capacitance | 10 pF |
| Input common mode | 400 mV |
Ports
inpinputinninputoutoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pin
Reference
X. Peng, W. Sansen, Transconductance with capacitances feedback compensation for multistage amplifiers, 2005. IEEE Journal of Solid-State Circuits, 40(7):1514-1520.
The transconductance with capacitances feedback compensation (TCFC): an outer Miller capacitor, and a feedback capacitor from the output into a common-gate current buffer on the second stage's output, with a feedforward output device. The core amplifier, its bias, the buffer's gate on the NMOS bias line and every size are this library's, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.