StrongARM latch comparator, PMOS input

How it works

The StrongARM latch turned upside down. While the clock is high it resets: the tail MT is off, and M7 to M10 hold both latch nodes and both input drains at ground. When the clock falls, MT turns on and the input pair charges x1 and x2, the side with the lower input faster; M3 and M4 pass that on to o1 and o2, and once those rise far enough the two cross-coupled inverters regenerate the difference until one node is at the supply and the other back at ground. A PMOS pair supports inputs near ground, where an NMOS pair would be off. There is no intentional static bias path, but leakage remains.

No bias current: MT is a switch on clk. The bench clocks the latch at 250 MHz from 1.2 V with both inputs near 0.3 V; each decision takes about 170 fJ from the supply, and in reset only leakage flows. MT is narrow on purpose: it limits the current while the pair integrates, so the pair's source settles well below V_DD, the pair is less strongly inverted, and its g_m/I_D - the gain it builds before the latch takes over - is higher.

Signal path

• Reset (M7, M8, M9, M10): While clk is high they hold o1, o2, x1 and x2 at ground with the tail off. Reset erases the old decision; there is no intentional static bias path, but leakage still flows.
• Input integration (MT, M1, M2): clk falling turns MT on; M1 on inp and M2 on inn charge x1 and x2, the lower input's side faster, turning the overdrive into a growing difference.
• Regeneration (M3, M4, M5, M6): M3 and M4 pass the charge on to o1 and o2; as those pass V_TN, M5 and M6 join in, and the cross-coupled pairs amplify the gap until one node reaches V_DD and the other returns to ground.
• Output buffers (M11, M12, M13, M14): Inverters on o1 and o2: both outputs are high while the latch resets, and the one on the losing side falls - outp stays high when inp is above inn.

Key relations

• Regeneration: ΔV(t) = ΔV_0·e^(t/τ), τ ≈ C_o/(g_m3 + g_m5). C_o is o1 or o2, the buffer's gate included; about 60 ps at tt
• Decision time: t_dec ≈ t_0 + τ·ln(V_DD/(2 G V_id)). each decade less overdrive costs τ·ln 10, about 0.14 ns
• Integration gain: G ≈ (g_m/I_D)_1 · |V_TP|. the gain the input pair builds on x1 and x2 before M3 and M4 conduct; a strongly driven pair builds little
• Offset: σ_os² ≈ 2σ_VT,1² + 2(s_3 σ_VT,3)² + 2(s_5 σ_VT,5)². s_3 and s_5, measured by shifting one device's threshold at a time, are about 0.5 and 0.3: the latch's mismatch is divided by the gain the input pair integrates first; about 3.3 mV σ in all
• Input common mode: V_CM + |V_TP| < V_t. the pair must conduct from the tail's node: it decides with its inputs anywhere from ground to about 0.6 V, where an NMOS pair would need its inputs well above V_TN

Trade-offs

• Tail width (Wt): a stronger tail integrates faster but drives the pair harder, lowering its g_m/I_D and the gain it integrates, so the latch's own mismatch counts for more. With an 8 µm tail and a minimum-length latch the offset was 8 mV σ at 0.3 ns; the 2 µm tail and 0.2 µm latch give 3.5 mV at 0.63 ns.
• Latch length (L): at the minimum length each device's threshold moves with its drawn length, a mismatch no width averages away; 0.2 µm makes it small, at some regeneration speed.
• Input pair (Wi, Li): larger lowers its own mismatch and raises its g_m/I_D, but loads x1, x2 and whatever drives the inputs - 24 µm bought 12 % less offset for 13 % more delay.
• Input common mode (VCM): the latch decides from ground to about 0.6 V - 0.69 ns at 10 mV with the inputs at 0 V, 0.63 ns at 0.3 V, 0.96 ns at 0.6 V; above that the pair runs out of V_SG from the tail's node and the smallest inputs no longer resolve in time.

Testbenches and limits

• Decided states: Six decisions, alternately either way at a clear overdrive: the output levels, the level in reset, and the charge each decision takes from the supply.
• Thresholds: V_id stepped from -30 mV to +30 mV and back, one level per clock cycle over 120 cycles: where the decisions turn each way. A latch that keeps something of its last decision turns late each way - hysteresis.
• Decision time: The thresholds found first; then, for each overdrive from 1 mV to 100 mV, one decision each way past them, timed from the clock edge to the output at half the supply. 8 runs.

Design variables and defaults

Ports

• inp input (+)
• inn input (-)
• clk clock: high resets, low decides
• outp output
• outn output
• vdd supply
• vss ground

Reference

T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture, 1992. 1992 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 28-29.

The latch: an input pair under a cross-coupled pair, a clocked tail, and reset switches on every internal node, drawing charge only as it decides. The complementary form - PMOS input, reset to ground, decision on the clock's falling edge - the output buffers and the sizing are this library's, for SG13G2 at 1.2 V.