Beta-multiplier reference

How it works

A bias current set by a resistor and a ratio of transistors rather than by the supply. M1 is diode-connected; M2, K copies of M1 with R1 in its source, carries the same current at a smaller V_GS, and only one non-zero current makes V_GS1 = V_GS2 + I·R1. The PMOS pair closes the loop. In the regulated topology an amplifier holds M2's drain at M1's reducing the drains' supply dependence, and a start-up circuit removes the other solution, zero current.

No external reference: the loop settles at the one non-zero current for which V_GS1 = V_GS2 + I·R1, set by R1 (10 kΩ by default) and K (4 by default); vbn and vbp pass copies of it to other circuits.

Signal path

• Start-up (MS1, MS2, MS3): With no current vbn is low, MS2 is off, MS3 pulls su up and MS1 pulls the PMOS gates down; once vbn rises MS2 turns MS1 off.
• Self-biased core (M1, M2, R1): M1 is diode-connected; M2, K copies of M1 at the same current, needs less V_GS, and R1 in its source drops the difference.
• PMOS mirror (M3, M4): Share the gate vbp and force one current through both branches: M3 into M1, M4 into M2; in the basic topology M4 is the diode.
• Regulating amplifier (MT, MA1, MA2, MA3, MA4): Compares M2's drain (non-inverting) with vbn and drives vbp until they are equal, reducing the drains' supply dependence; its tail copies M1.
• Compensation (CC, RZ, CZ): C_c on vbp sets the dominant pole; R_z and C_z across the amplifier's inputs lower M2's drain impedance at high frequency without touching the bias.

Key relations

• Self-bias condition: V_GS1 = V_GS2 + I · R1. M2 is K copies of M1 at the same current, so it needs less V_GS
• Reference current: I = 2 (1 − 1/√K)^2 / (µ_n C_ox (W/L)_1 R1^2). strong inversion: no V_DD appears; mobility does, and it falls with temperature, so I rises faster than PTAT
• Loop gain near zero current: A_loop(I → 0) ≈ K. ideal local-loop intuition, not a start-up guarantee; the regulated amplifier has no tail current at zero
• Regulation: V_d2 = V_bn. the amplifier gives M3 and M4 one drain voltage, so the PMOS copy error from unequal drain voltages is reduced

Trade-offs

• R1: current falls with its square in strong inversion; a larger R1 saves power but costs area and edges the devices towards weak inversion.
• K (M2 = K copies of M1): larger K raises the current and the loop's gain near zero current, and costs area.
• Topology: regulation holds M2's drain at M1's and cuts supply sensitivity, but adds a loop to compensate and can remain in its off state without MS1 to MS3.
• C_c, R_z, C_z: C_c alone leaves almost no phase margin; R_z–C_z across the amplifier's inputs restores it; without C_z the loop rings.

Testbenches and limits

• Against the supply
• Against temperature
• Power-up
• Supply step

Design variables and defaults

Ports

• vbn output: the NMOS bias: a copy of M1 sinks I_ref
• vbp output: the PMOS bias: a copy of M3 sources I_ref
• vdd supply
• 0 ground

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017. Bandgap References - supply-independent biasing: the self-biased circuit with a resistor in the source of the wider device, and its start-up.

The topology, the current it settles at, and the zero-current state a start-up circuit removes. The amplifier that holds M2's drain at M1's is the op amp a bandgap uses to hold two nodes equal (same chapter), applied to this loop.

• R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd ed., 2010