Charge-redistribution DAC

How it works

Turns a digital code into a voltage by charge sharing: the array at the heart of a SAR converter. Each bit drives the bottom plate of a binary-weighted capacitor to V_ref or ground, and the common top plate settles at the capacitance-weighted average of the bottom plates, ideally V_ref·code/2^N. Exact linear capacitors give equal ideal steps. Mismatch changes their relative sizes; a linear, code-independent top-plate capacitance mainly scales the transfer, without changing endpoint-fit linearity after gain error is removed. The deck represents equivalent square MIM capacitors; an identical-unit physical array remains a layout recommendation, not an implemented layout.

Nothing is biased: charge sharing alone sets the output, with V_ref (1.2 V by default) the only reference, applied by the bench's drivers. Rt holds the floating top plate at 0 V at DC, and its time constant, milliseconds, is far longer than the sweep.

Signal path

• Bit drivers (Vb0..VbN-1): The bench's sources count in binary, one code per nanosecond, switching each bottom plate b_k between ground and V_ref, so one transient walks every code.
• Binary array (C0..CN-1): Capacitor k is 2^k·C_unit, its mismatch drawn as for 2^k unit cells; moving its bottom plate by V_ref moves the top plate by V_ref·C_k/C_total.
• Termination (Cterm): One more unit to ground makes the ideal array total 2^N·C_unit. With exact ratios and negligible extra top-plate capacitance, each step is V_ref/2^N and full scale is V_ref·(2^N − 1)/2^N.
• Top plate (Cpar, Rt): The shared top plate is the output; Cpar, zero by default, is an ideal surrogate for capacitance to ground, and Rt, 10 GΩ, only gives the simulator a DC path. Neither is a separately validated physical device to copy into a layout.

Key relations

• Output: v_top = V_ref·Σ b_k·C_k/(C_total + C_par). ideal linear charge sharing; with exact units and C_par = 0, V_ref·code/2^N. Physical parasitics and transient measurement can leave residual error.
• LSB: LSB = V_ref·C_u/(2^N·C_u + C_par). 18.75 mV at the defaults; C_par shrinks every step alike, a gain error
• Unit-cell spread: σ_C,k/C_k = σ_u/√(2^k). σ_u is Unit-cap σ; 2^k cells average, yet the MSB has the largest absolute error
• DNL at mid-scale: σ_DNL ≈ σ_u·√(2^N − 1). in LSB: at the MSB transition the largest capacitor is exchanged for all the others
• Total capacitance: C_total = 2^N·C_u. 1.28 pF at the defaults; it doubles per bit, in area and drive energy

Trade-offs

• Resolution: each extra bit halves the LSB and doubles C_total, while the DNL spread at the MSB step grows as √(2^N).
• C_unit: alone it cancels from the ratio; a larger unit shrinks the top-plate parasitic's gain error and, on silicon, mismatch, at the cost of area.
• Fixed linear top-plate capacitance: scales every code by 2^N·C_u/(2^N·C_u + C_par), costing full scale while leaving endpoint-fit DNL and INL approximately unchanged after gain error is removed. Voltage-dependent or code-dependent parasitics need separate analysis.
• Unit-cap σ: DNL and INL scale with it; the worst DNL is at the MSB transition, and below −1 LSB a step runs backwards.

Testbenches and limits

• Transfer and linearity

Design variables and defaults

Ports

• top output: common top plate
• b0..bN-1 control: bottom plates, driven to V_ref or ground
• 0 ground: termination capacitor and substrate reference

Reference

J. L. McCreary and P. R. Gray, All-MOS charge redistribution analog-to-digital conversion techniques - Part I, IEEE Journal of Solid-State Circuits, vol. SC-10, no. 6, 1975. the binary-weighted array, its termination capacitor and the effect of top-plate parasitic.

The array itself, and the separation this bench measures: parasitic costs full scale, mismatch costs linearity.