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Cascode current mirrors

Copies a current more accurately as the output voltage changes. A transistor stacked above the output device keeps its drain voltage nearly constant. This improves output resistance but needs extra voltage; the wide-swing option recovers some range using a second reference current.

How it works

A current mirror with a second transistor stacked on the output device. The cascode M4 holds M2's drain nearly still while the output moves, so M2's current changes less with the output and the output resistance rises by M4's intrinsic gain, g_m4 r_o4. The price is headroom: two stacked diodes put the reference input two V_GS up. The wide-swing topology biases the cascodes from a separate stack instead, buying most of that swing back for a second reference current.

One I_ref (10 µA by default) sets every gate, and every device is a copy of one unit, 4 µm/2 µm by default, so equal drain voltages improve its nominal copy accuracy; the wide-swing topology draws a second I_ref for its bias stack. Feed that additional reference current into vb in the wide-swing option; it is supplied by the bench, not generated inside the mirror.

Signal path

  • Reference stack (M1, M3): I_ref flows through M3 into M1, setting M1's V_GS; in the cascode topology both are diodes, which puts ref two V_GS above ground.
  • Output device (M2): Shares M1's gate, so it approximately copies I_ref; matching drain voltages reduces systematic error.
  • Output cascode (M4): Its gate tied to M3's, it holds M2's drain at M1's while the output moves, multiplying M2's r_o by g_m4 r_o4.
  • Wide-swing bias (Mb1..MbK): Wide-swing only: a second I_ref through K unit devices in series sets vb, a V_GS plus about one overdrive, for both cascode gates.

Key relations

  • Output resistance: R_out ≈ g_m4 r_o4 · r_o2. against r_o2 for the simple mirror; holds only while M2 and M4 are both saturated
  • Compliance, cascode: V_out,min ≈ V_GS1 + V_GS3 − V_TH4 ≈ V_TH + 2 V_ov. the reference input sits two V_GS up, a threshold more than the devices need
  • Compliance, wide-swing: V_out,min ≈ √K · V_ov. square law, with M2 left at V_DS2 ≈ (√K − 1) V_ov: K = 4 is the edge of saturation
  • Bias stack: V_b ≈ V_TH + √K · V_ov. K units in series approximate a longer device; body effect and finite drain voltages modify the result; moderate inversion needs K above 4 (6 by default)

Trade-offs

  • Topology: cascode multiplies R_out by about g_m r_o over simple but costs a threshold of headroom; wide-swing buys most back for a second I_ref.
  • Bias stack, units in series: fewer units lower the knee but push M2 out of saturation, so R_out falls; more units waste swing.
  • L (unit): longer raises r_o, which enters the cascode's R_out twice, but raises V_ov and every knee with it, and costs area.
  • I_ref: more current raises V_ov, moving every knee up, and lowers r_o, so R_out falls.

Testbenches and limits

  • Output characteristic

Design variables and defaults

VariableDefault
Topologycascode
I_ref10 µA
W (unit)4 µm
L (unit)2 µm
Bias stack, units in series6

Ports

  • ref input: carries I_ref
  • out output
  • vb bias: wide-swing option only: inject a second I_ref into the Mb1..MbK cascode-bias stack; unused in the simple and cascode options
  • vdd supply
  • 0 ground

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017. Current Mirrors - cascode current mirrors, and the low-voltage cascode that biases the cascodes separately.

The two topologies, the output resistance a cascode gives (about g_m r_o times the output device's r_o), and the headroom each needs.

  • T. Chan Carusone, D. A. Johns and K. W. Martin, Analog Integrated Circuit Design, 2nd ed., 2012

IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.