Chopper OTA core, common mode set from outside

How it works

The OTA of a capacitively coupled chopper amplifier, on its own. A PMOS pair feeds a folded cascode whose outputs o1, o2 are its high-resistance nodes; a chopper between the stages - held straight in every bench here - would swap o1 and o2 at the chopping frequency, and a Miller-compensated common-source stage gives the gain and the swing. The core has no common-mode loop of its own: its loads copy the diode ML on pin cmc, and the benches close an ideal loop that draws Ib from ML and 50 µA more per volt the output common mode stands above vocm.

The testbench draws Ib = 5 µA out of the diode MB. MT is two copies of it (10 µA); MB1 copies Ib into the NMOS diode MB2, which M3 and M4 copy twice (10 µA each). The cascode gates come from long, narrow diodes carrying Ib: MB6 stands one cascode V_GS plus about 0.2 V above ground, the room M3 needs under M5, and MB3 likewise leaves M7 room under M9 - differences that grow with temperature, as V_DSAT does, where a poly resistor's drop would shrink. o1 and o2 settle at the gate voltage M11 needs for N2·Ib = 20 µA, about 0.5 V, close to where its V_GS stops moving with temperature. Drawn at Ib, ML stands at the gate voltage the loads need, so the ideal loop only supplies the few-percent correction and the output common mode stays within about 15 mV of vocm at every corner.

Signal path

• Input pair (M1, M2, MT): MT's 10 µA divides between M1 and M2 as the inputs differ; a rise on inp takes current away from the fold node f1.
• Folded cascode (M3, M4, M5, M6, M7, M8, M9, M10): M3, M4 sink 2·Ib each; what the pair does not supply there is drawn through the NMOS cascodes M5, M6 from o1, o2, where the loads M7, M8 under the PMOS cascodes M9, M10 source Ib. Cascoded on both sides, o1 and o2 are the amplifier's high-resistance nodes, and a rise on inp pulls o1 down.
• Output chopper (SO1, SO2, SO3, SO4): With clk high, SO1 and SO2 join o1 to g1 and o2 to g2; clocked, SO3 and SO4 cross them every other half period, so a chopped signal returns to baseband at g1, g2 while the first stage's offset and 1/f noise leave at the chopping frequency. Every bench of this OTA holds it straight.
• Second stage (M11, M12, M13, M14, CC1, CC2, RZ1, RZ2): M11, M12 invert g1, g2 onto outp, outn against the sources M13, M14, so outp follows inp. CC1, CC2 across them, in series with RZ1, RZ2, make g1, g2 the dominant pole.
• Common-mode control (ML, M7, M8): M7, M8 copy the current drawn out of ML. The bench's ideal loop draws Ib and more as the output common mode rises: the loads then source more, o1, o2 rise, and M11, M12 pull the outputs back down.

Key relations

• Differential gain: A_d ≈ g_m1·R_o1·g_m11·(r_o11 ∥ r_o13). R_o1 is the cascoded resistance at o1, set mostly by the NMOS side (g_m5·r_o5·r_o3); about 78 dB with the chopper held.
• Unity-gain frequency: ω_u ≈ g_m1/C_c. About 4.5 MHz: g_m1 ≈ 92 µS, C_c = 3 pF. The closed-loop response depends on the feedback network; the complete clocked amplifier must settle within each half-period at its selected gain and chopping frequency.
• Compensation zero: ω_z = 1/[C_c·(R_z − 1/g_m11)]. R_z = 12 kΩ is above 1/g_m11 ≈ 7 kΩ, so the zero lies in the left half-plane, near 11 MHz, and adds phase at ω_u: the margin is close to 90°.
• Headroom under o1: V_GS,11 ≥ V_DS,3 + V_DS,5. About 0.5 V against 0.2 V for M3 and 0.3 V for M5, both near weak inversion, where V_DSAT is about 4kT/q.
• Common-mode loop: ω_u,cm ≈ (g_cm/g_m,ML)·g_m7/C_c. g_cm = 50 µS is the bench loop's; the loop runs through both stages and the Miller capacitors, like the differential path, and settles in about 230 ns without overshoot.

Trade-offs

• Miller capacitor (Cc): larger adds margin for a heavier feedback network, but slows the OTA and its recovery after each chopper edge.
• Second-stage current (N2): more raises g_m11, the output pole and the slew rate into the load, at the supply's cost; o1, o2 do not move, since M11's unit sets them.
• Second-stage unit (W2, L2): a lower V_GS, from a wider or shorter unit, leaves less room for M3 and M5 under o1, o2; a higher one crowds M7 and M9 above them.
• Cascode-bias diodes (Wdn, Wdp): they share the room between each current source and its cascode; a narrower diode gives the source more and the cascode less.

Testbenches and limits

• Operating point, chopper held: The amplifier as a fully differential follower at its input common mode, its chopper held straight: the current it draws, where its outputs sit, and the difference they settle at with no input.
• Open-loop gain, chopper held: Differential gain and phase with the follower's loop closed only at DC, through a 1 TH coil: every frequency the sweep visits sees the open loop, and the operating point is the follower's. The chopper is held straight.
• Step response, chopper held: A 200mV differential step into the follower, its chopper held: how fast the output difference follows and whether it rings - the test that finds a local loop an open-loop phase margin hides.
• Common-mode loop, chopper held: A 50 mV step on the common-mode reference: the output common mode has to follow it, and how it gets there - its settling and its overshoot - is the common-mode loop's phase margin, a loop the differential benches never see.
• Noise, chopper held: Noise referred to the differential input of the follower, its chopper held: the density at 1 kHz and the total from 1 Hz to 1 MHz. Held, the first stage's 1/f noise is all here; clocked, the chopper moves it up to the chopping frequency.

Design variables and defaults

Ports

• inp input
• inn input
• outp output
• outn output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin
• cmc bias: common-mode control: the diode ML that the first-stage loads M7, M8 copy; a CMFB draws Ib from it, plus its correction - here the bench's ideal one
• clk clock: high: the output chopper straight
• clkb clock: high: the output chopper crossed

Reference

Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa, A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes, 2011. IEEE Journal of Solid-State Circuits, 46(7):1534-1543.

The OTA's architecture: a PMOS-input folded-cascode first stage, the output chopper placed between the two stages, a Miller-compensated second stage. The sizing, the bias network and the cascode biasing are this library's, for SG13G2 at 1.2 V.