Differential chopper, transmission gates

How it works

Multiplies a differential signal approximately by a square wave of +1 and −1: the modulator at each end of a chopper amplifier. While clk is high the straight transmission gates pass inp to outp and inn to outn; while clkb is high the crossed gates swap them, so the output difference changes sign every half period. Each gate combines NMOS and PMOS devices to improve conduction across the supply range. Complementary clocks alone do not guarantee non-overlap throughout that range: simultaneous straight and crossed conduction near an edge can temporarily connect the inputs.

Nothing is biased: clk and clkb, complementary between 0 and V_DD, choose which gates conduct. At mid-supply, the worst place, each half has about 0.1 V of overdrive past its threshold and body effect; the benches chop at 20 kHz into 100 kΩ and 1 pF returned to 0.6 V.

Signal path

• Straight gates (S1n, S1p, S2n, S2p): On while clk is high: inp to outp and inn to outn, so the output difference is the input's, less what R_on drops into the load.
• Crossed gates (S3n, S3p, S4n, S4p): On while clkb is high: inp to outn and inn to outp, so the output difference is the input's, inverted.
• Edges (S1n, S1p, S3n, S3p): At each edge the outgoing gates release channel charge and couple the clock into the signal nodes. Matching helps make the disturbance common to both outputs, but signal dependence, mismatch, skew and overlap can leave a differential error.

Key relations

• Modulation: v_out,d(t) = m(t)·v_in,d(t), m = ±1. The clocked bench reads the crossed phase over the straight one: −1.000.
• Chopping spectrum: m(t) = (4/π)·Σ sin(n·ω_ch·t)/n, n odd. A signal moves to f_ch ± f, 3f_ch ± f and on; a second chopper in step brings it back.
• Loss into a load: A = R_L/(R_L + R_on), R_on = R_on,n ∥ R_on,p. About 2.3 kΩ at mid-supply: 2 % into 100 kΩ, the same in both phases when the four gates match.
• Residual offset: V_os,res ≈ 2·f_ch·τ·ΔV_spike. Only the difference between the two sides' edge spikes survives demodulation: a matter of the gates' match.

Trade-offs

• Switch width (Wsw): wider lowers R_on and the loss into a load, but releases more channel charge at every edge and loads the clock more.
• Switch length (Lsw): minimum length gives the least R_on for the least channel charge; a longer gate only adds both.
• PMOS-to-NMOS ratio (fixed at 2): it sets where across the range R_on peaks and how the two halves' charges cancel.

Testbenches and limits

• On-resistance, one phase held: The clocks held straight, a 10uA current drawn through the switch from inp to outp while inp is swept across the supply: its on-resistance at every level a signal can take. The other input sits at mid-supply.
• Clocked into a load: The clocks running, a DC difference on the inputs, each output loaded by a resistor and a capacitor to mid-supply: the output difference must swap sign every half period with the same size, less only what the switches drop into the load.

Design variables and defaults

Ports

• inp input
• inn input
• outp output
• outn output
• clk clock: high: straight, inp to outp and inn to outn
• clkb clock: high: crossed, inp to outn and inn to outp
• vdd supply
• vss ground

Reference

C. C. Enz, G. C. Temes, Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization, 1996. Proceedings of the IEEE, 84(11):1584-1614.

The chopper as a multiplier by a ±1 square wave, and why its residual offset comes from the charge its switches release at the edges. The transmission-gate cell, its sizing and its benches are this library's, for SG13G2 at 1.2 V.

• Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa, A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes, 2011