Resistive common-mode detector

How it works

R1 and R2 form a weighted average of the two input voltages. Equal realized resistors give the arithmetic mean; mismatch allows differential signal into the sensed common mode. C1 and C2 bypass the resistors at high frequency, reducing the load capacitance's effect rather than eliminating it. For equal R and C and a load C_L, the ideal common-mode transfer is (1 + sRC)/(1 + sR(C + C_L/2)); it has a pole-zero shelf, not a perfectly flat response.

At DC, neglecting leakage and sensing-node loading, only the differential input drives current through the two series resistors. Changing voltages also move charge through the capacitors. out reports whatever common mode the inputs carry; holding it at a target is the job of the error amplifier it feeds.

Signal path

• Averaging divider (R1, R2): R1 from inp and R2 from inn meet at out; with equal values out settles at the mean of the two inputs.
• Fast path (C1, C2): The capacitors across the resistors average at high frequency too, so out follows the common mode past the corner the resistors would make with the load.

Key relations

• Sensed common mode: V_out = (V_inp·R2 + V_inn·R1)/(R1 + R2). The arithmetic mean for equal realized resistors. A shared nominal value does not remove random mismatch.
• Mismatch error: ΔV_cm = V_out − (V_inp + V_inn)/2 = (R2 − R1)·(V_inp − V_inn)/(2·(R1 + R2)). Resistor mismatch lets a fraction of the differential signal into the sensed common mode.
• High-frequency division: V_out/V_cm → 2C/(2C + C_L). The load leaves a pole-zero shelf: the ideal response changes from one at DC to 2C/(2C + C_L) at high frequency. The recorded bandwidth uses a 3 dB criterion, not a 1 dB flatness guarantee.
• Differential load: R_in,d = R1 + R2. Seen between the two outputs: 1 MΩ by default.

Trade-offs

• Resistor value: larger loads the stage's outputs less, but takes more area, and without the capacitors would lower the sensing bandwidth.
• Resistor length: longer strips match better, so less of the differential signal leaks into the sensed common mode.
• Capacitor value: larger keeps the division by the load closer to one, and adds capacitance to the outputs.

Testbenches and limits

• Transfer: The sensed common mode swept from 0 to 1.2 V, with the two inputs equal and then 200m V apart either way: the output against it, its slope where the inputs sit at the reference, and whether a difference between them moves it.
• Bandwidth: A small common-mode signal on both inputs and the output driving its load: how fast the sensed common mode follows.

Design variables and defaults

Ports

• inp input: one of the two outputs it senses
• inn input: the other
• out output: their average: the sensed common mode
• vss ground: the substrate under the resistors

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd, McGraw-Hill, 2016. Sec. 9.7 (common-mode feedback: resistive sensing, and capacitors across the sensing resistors).

The technique: resistive averaging of the two outputs, with capacitors in parallel with the resistors to reduce the attenuation and phase lag caused by the error amplifier's input capacitance. The values, the choice of high-resistance poly and MIM, and the targets are this library's, for SG13G2.