Five-transistor CMFB, PMOS input

How it works

A common-mode feedback block for a fully differential stage: it senses the average of two outputs and returns a control voltage that rises when that average rises above ref. Two equal resistors form the average without responding to the outputs' difference, and a five-transistor amplifier with a PMOS pair on an NMOS mirror amplifies the error. At balance its output rests at the mirror diode's gate voltage, the level of an NMOS current sink's gate.

MT carries 2 Ib, so each side of the pair carries Ib at balance and out rests at M3's gate voltage at that current, about 0.36 V. The pair's n-wells sit on their sources, which keeps its V_SG small and the tail saturated with the sensed common mode near 0.5 V. Built to set NMOS sinks, the block works best into a diode whose copies they are: its output current then sets their current directly, and its benches close the loop that way.

Signal path

• Detector (RS1, RS2): The equal resistors put the average of inp and inn on sen; a purely differential swing leaves sen still.
• Error amplifier (M1, M2, M3, M4): M1, gate on sen, and M2, gate on ref, split the tail; the mirror M3, M4 subtracts the halves at out, which rises as sen rises above ref.
• Tail (MB, MT): The bench draws Ib out of the diode MB, and MT, two copies, feeds the pair.

Key relations

• Sensed common mode: V_sen = (V_inp + V_inn)/2. Each input sees one resistor to a node that stays still for differential signals.
• Servo gain: A_s = ΔV_out/ΔV_sen ≈ g_m1·(r_o2 ∥ r_o4). Positive: out follows the sensed common mode, so the devices it drives must pull the outputs down as it rises.
• Balanced output: V_out,bal ≈ V_GS3(I_T/2). At zero error the halves match and M4 copies M3.
• Detector pole: f_s ≈ 1/(2π·(RS/2)·C_gs1). Must sit well above a closed loop's crossover: a small pair and 200 kΩ resistors put it near 30 MHz.

Trade-offs

• Detector resistors: larger load the sensed outputs less, but pull the detector pole down with the pair's gate capacitance.
• Pair width: wider lowers offset and raises the gain, but loads sen and narrows the linear window.
• Mirror length: longer raises the servo gain, but slows its output pole and adds capacitance.
• Tail current: more speeds the servo for more supply current.

Testbenches and limits

• Transfer: The sensed common mode swept from 0 to 1.2 V, with the two inputs equal and then 200m V apart either way: the output against it, its slope where the inputs sit at the reference, and whether a difference between them moves it.
• Servo response: A small common-mode signal on both inputs and the output driving its load: the servo's gain at DC, its bandwidth and its unity-gain frequency.
• Common-mode loop: The block holding the common mode of its plant: where that common mode lands against the reference, and the loop's gain and phase margin, measured by Middlebrook's double injection - a voltage, then a current - where the block's output meets the plant.
• Common-mode kick: The loop kicked: 2uA into each of the plant's outputs for 50ns, and how the common mode comes back.

Design variables and defaults

Ports

• inp input: one of the two outputs it senses
• inn input: the other
• out output: the control voltage: rises with the sensed common mode
• vdd supply
• vss ground
• ref bias: the common mode to hold
• ib bias: the reference current, drawn out of this pin

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd, McGraw-Hill, 2016. Sec. 9.7 (common-mode feedback: resistive sensing and the error amplifier).

The technique: resistive common-mode sensing, which averages the outputs without responding to their difference, and a differential-pair error amplifier comparing the average with a reference to set a stage's current sources. The PMOS-input five-transistor amplifier, its sizing, the plant it is tested around and the targets are this library's, for SG13G2 at 1.2 V.