Switched-capacitor CMFB

How it works

CC1 and CC2 continuously couple the sensed outputs to the control node, but they do not provide a DC conductive path: stored charge sets the control level. During phase 1, CS1 and CS2 charge to ref − vbias. During phase 2, they share that charge with the sensing capacitors. With ideal switches, negligible loading and settled clocking, out approaches vbias plus the sensed common mode minus ref. Leakage, charge injection and load capacitance cause departures from that approximation.

There is no intentional static bias path in the sensing block. Clock switching moves charge, device leakage remains, and the two clock phases must not overlap. ref is the common mode to hold and vbias the control voltage the stage needs at that point: here the gate voltage at which one unit of the stage's sinks carries its current with its drain near the reference, which the bench makes with a replica. The switches on out and vbias are NMOS only, since those nodes sit a few hundred millivolts above ground.

Signal path

• Sensing capacitors (CC1, CC2): Each connects an output to out at every instant: out moves with the outputs' common mode, and their difference cancels.
• Recharge, phase 1 (M1, M2, M3, M7, M8, M9, CS1, CS2): Transmission gates M1, M2 and M7, M8 tie one plate of each switched capacitor to ref; M3 and M9 tie the other to vbias, so each holds ref less vbias.
• Refresh, phase 2 (M4, M5, M6, M10, M11, M12): M4, M5 and M10, M11 tie the capacitors to inp and inn, M6 and M12 to out: each switched capacitor sits across a sensing one and shares its charge, pulling it towards ref less vbias.

Key relations

• Steady state: V_out → V_bias + (V_inp + V_inn)/2 − V_ref. A slope of one; with the common mode at ref, out rests at vbias.
• Settling per cycle: e_(k+1)/e_k ≈ C_C/(C_C + C_S). Ignoring load and parasitics, C_S = C_C/2 leaves two thirds of the stored-charge error after each refresh: twelve refreshes reduce it below 1 % of its initial value. The default step bench measures six cycles to 1 % of the full applied step because capacitive feedthrough supplies most of the change immediately.
• Common-mode error in a loop: ΔV_oc ≈ V_GS,needed − V_bias. The block adds no gain: the distance between vbias and the gate voltage the stage needs appears as common-mode error one for one.
• Load on the outputs: R_eq ≈ 1/(f_clk·C_S). Only for differential signals and common-mode errors: a settled common mode moves no charge.

Trade-offs

• Switched capacitor: larger closes more of the ideal stored error each cycle. It changes both switched charge and node capacitance, so clock ripple need not rise; inspect the measured waveform.
• Sensing capacitor: larger divides the switches' charge injection down, and loads the outputs more.
• Switch width: wider settles faster within each phase but injects more charge onto out.
• vbias: must be the stage's own operating gate voltage, since the block cannot correct a wrong one.

Testbenches and limits

• Clocked settling: The block is clocked on its own, first at balance then after a 50 mV common-mode step. Settling requires every remaining cycle sample to stay within 1%, with at least two observed in-band cycles.
• Clocked loop: The block holding its plant's common mode, clocked, from a start with that common mode away from the reference: where it lands, how soon it is within 1 mV, and the ripple the clock leaves on it.

Design variables and defaults

Ports

• inp input: one of the two outputs it senses
• inn input: the other
• out output: the control voltage: vbias plus the common mode's distance from ref
• vdd supply
• vss ground
• ref bias: the common mode to hold
• vbias bias: the control voltage the stage needs with its common mode at ref
• p1 clock: phase 1: the switched capacitors recharge
• p1b clock: phase 1, inverted, for the PMOS halves
• p2 clock: phase 2, not overlapping phase 1: the switched capacitors across the sensing ones
• p2b clock: phase 2, inverted

Reference

T. Chan Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd, Wiley, 2012. Sec. 7.6 (common-mode feedback circuits: the switched-capacitor detector).

The circuit: capacitors from the outputs to the control node that sense the common mode, and capacitors switched on two non-overlapping phases between the reference and the bias and across the sensing capacitors, which set the charge on them. The switch types, the sizing, the stage it is tested around, the bias replica and the targets are this library's, for SG13G2 at 1.2 V.