Comparator with hysteresis

How it works

A continuous-time comparator with two thresholds. Once its output has turned, it feeds a current back into its first stage that reinforces that state, and it turns back only past the other threshold. A slow or noisy input may cross the pair's balance point repeatedly. The gap between thresholds prevents repeated switching only while those fluctuations are too small to cross both thresholds; larger noise can still make the output chatter.

Ib, 10 µA, is fed into the diode MB, and the tail MT, two copies, gives the pair approximately 20 µA. A current-source tail reduces the dependence of g_m1 and hysteresis on input common mode while the source remains saturated; it does not remove headroom or mismatch errors. With the inputs at 0.6 V the tail node sits near 0.30 V. M3 is sized to balance d1 near mid-supply, where the first inverter turns: the nominal thresholds are about +10 and −10 mV, with about 30 µA supply current.

Signal path

• Input pair (M1, M2, MT): MT's tail current divides between M1, on inp, and M2, on inn: inp rising past inn takes current from M2.
• Mirror load (M3, M4): M3 turns M2's current into a gate voltage and M4 copies it onto d1, where M1's current meets it: d1 falls as inp rises past inn.
• Inverter chain (M5, M6, M7, M8, M9, M10): Three inverters, each F times the last, turn d1's swing into a full logic swing at out, high when inp wins.
• Hysteresis (M11, RH1, M12, RH2): With out high M11 connects RH1 from d1 to ground and sinks current; with out low M12 connects RH2 from vdd and feeds it: either way the present state is reinforced.

Key relations

• Hysteresis: V_hyst ≈ V_DD/(g_m1 R_H). R_H = RH1 = RH2: the pair must cancel (V_DD − V_M,1)/R_H at one threshold and V_M,1/R_H at the other; about 20 mV at tt
• Thresholds: V_T+ ≈ (V_DD − V_M,1)/(g_m1 R_H), V_T− ≈ −V_M,1/(g_m1 R_H). symmetric about zero when the first inverter turns at V_DD/2
• Systematic offset: V_os ≈ (V_DD − V_SG3 − V_M,1)/A_1, A_1 = g_m1 (r_o1 ∥ r_o4 ∥ R_H). zero at tt by the size of M3; the supply moves d1's balance twice as fast as V_M,1, about ±4 mV per 10 % of V_DD
• Decision time: t_d ≈ C_d1 ΔV_d1/(g_m1 V_od). V_od past the threshold; once the output starts to turn, the feedback completes it
• Temperature: V_hyst ∝ T/R_H(T). g_m1 falls as 1/T in weak inversion, and the high-resistance poly falls too: the hysteresis grows by half from 27 °C to 125 °C

Trade-offs

• Hysteresis resistors (RH): smaller widens the hysteresis, V_DD/(g_m1 R_H), and rejects more noise, but needs more overdrive to turn the output and draws more current through the switches.
• Tail current (N): more raises g_m1, which narrows the hysteresis for the same RH and speeds the decision, at more supply current.
• Mirror width (W3): sets d1's balance, and so centres the thresholds - at one supply only, since the balance follows V_DD one for one and the inverter's threshold half as fast.
• Input pair (W1, L1): larger lowers the random offset, 2 to 3 mV σ, but adds capacitance at d1 and slows every decision.

Testbenches and limits

• Decided states: The comparator with its input well past its thresholds, each way: the output levels and the current it draws in each state.
• Thresholds: V_id swept slowly across its thresholds, up and back down: where the output flips each way, the hysteresis between them, and the offset at their midpoint.
• Decision time: The thresholds found first; then, for each overdrive from 1 mV to 50 mV, a step past each of them from 100 mV the other side, timed to the output at half the supply. 7 runs.

Design variables and defaults

Ports

• inp input (+)
• inn input (-)
• out output
• vdd supply
• vss ground
• ib bias: the reference current, fed into this pin

Reference

P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press, 2002. Ch. 8 'Comparators' (Secs. 8.1 Characterization, 8.2 Two-Stage Open-Loop Comparators, 8.4 Improving the Performance of Open-Loop Comparators).

The comparator's characterization - thresholds, hysteresis, propagation delay against overdrive - and its structure: a differential pair on a current-mirror load, gain stages to a logic swing, and positive feedback that splits one threshold into two. The feedback through output-switched resistors into the first stage's output, the bias and the sizing are this library's, for SG13G2 at 1.2 V.