Common-source amplifier

How it works

M1's small-signal transconductance converts a change in gate voltage to drain current. The output resistance is the load resistor in parallel with the transistor's output resistance. Their product sets the low-frequency gain; bias and parasitic capacitance also affect bandwidth.

V_GS bias, 0.32 V by default, sets M1's drain current; R_D (20 kΩ by default) turns it into V_out = V_DD − I_D R_D, which the bias-point analysis places near V_DD/2 so M1 stays saturated with room to swing.

Signal path

• Input transistor (M1): Common source: the V_GS bias plus the signal on its gate set its drain current, and g_m1 converts input voltage to current.
• Load resistor (Rd): From vdd to out, it turns M1's current into V_out = V_DD − I_D R_D, so the output falls as the input rises.
• Load capacitance (Cl): At the output, it slows voltage changes. Together with device and resistor parasitics, it sets the dominant output pole.

Key relations

• Small-signal gain: A_v ≈ −g_m1 (R_D ∥ r_o1). only while M1 is saturated; the minus sign is the inversion, so the phase starts at 180°
• Bandwidth: f_3dB ≈ 1 / (2π (R_D ∥ r_o1) C_total). dominant-output-pole approximation; C_total includes the load and output parasitics
• Gain-bandwidth product: GBW ≈ g_m1 / (2π C_total). approximately independent of R_D only while transconductance and total output capacitance remain fixed; changing R_D also changes the real circuit's bias and parasitics
• Saturation limit: V_out = V_DD − I_D R_D > V_GS − V_TH. below this M1 enters triode and the gain collapses; the DC transfer shows where

Trade-offs

• R_D: usually more gain and less bandwidth. Their product is only approximately constant at fixed transconductance and capacitance; recheck the bias, since a larger resistor also pulls V_out down.
• V_GS bias: more current raises g_m1 and the gain-bandwidth product but lowers V_out; too high and M1 enters triode, too low and it barely conducts.
• L: longer raises r_o1, lifting the gain's ceiling g_m1 r_o1, but passes less current at the same V_GS bias and adds capacitance.
• C_L: a larger load lowers the bandwidth and the gain-bandwidth product together and leaves the DC gain untouched.

Testbenches and limits

• Bias point: Choose V_GS from this curve before reading the gain.
• Frequency response

Design variables and defaults

Ports

• in input
• out output
• vdd supply
• 0 ground

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017. Single-Stage Amplifiers - the common-source stage with resistive load.

The topology and the small-signal result Av = -gm*(RD || ro), which is what the r_o-limited behaviour below is measured against.