Cascode common-source stage

How it works

The input transistor converts voltage to current. Cascodes raise the effective resistance of both output branches, so their parallel combination gives a larger voltage gain. A feedback loop is needed to set the high-gain stage's DC operating point; the testbench supplies that loop.

The testbench draws Ib, 10 µA, out of the ib pin through MB and Rp. M4 and M3 use four PMOS units against MB's two, targeting 20 µA in the output branch; M5 targets 5 µA in the NMOS ladder. The measured total is about 34.5 µA at nominal and varies slightly across the checked corners. The testbench servo sets the input near 0.30 V at TT while holding the output 0.55 V below the supply. This bias keeps the stacked devices in saturation at the checked default conditions; it does not validate every editable setting.

Signal path

• Input device (M1): Common source: in sets its drain current, and g_m1 is the stage's transconductance. It is long, 2 µm, so that r_o1 - the resistance the NMOS cascode multiplies - is high.
• NMOS cascode (M2): Common gate, from nc: it passes M1's current to out while holding x, M1's drain, still, which multiplies r_o1 by g_m2 r_o2.
• Load (M4, M3): M4 sources N copies of the reference into y; M3, its cascode, with its gate on ib, holds y still and raises the load's output resistance the same way.
• PMOS ladder (MB, Rp): Ib, drawn out of the ib pin, flows through the diode MB and then Rp: pg sets M4's gate, and ib, Ib·Rp below it, sets M3's - so M4 is left about Ib·Rp across it.
• NMOS ladder (M5, MNb, Rn): M5 feeds Ib/2 into the diode MNb over Rn. MNb runs at M2's current density, so the two share a V_GS, and M2 holds M1's drain at the drop across Rn.

Key relations

• Output resistance, NMOS side: R_out,n ≈ (g_m2 + g_mb2) r_o2 · r_o1. M1's r_o multiplied by the cascode's intrinsic gain: the weaker side, and so the one that sets the gain
• Output resistance, PMOS side: R_out,p ≈ (g_m3 + g_mb3) r_o3 · r_o4. the load, cascoded the same way: several times R_out,n, the PMOS devices' intrinsic gain being much the higher
• Gain: A_v ≈ −g_m1 (R_out,n ∥ R_out,p). about 920 V/V, 59 dB, at tt; 125 °C lowers every g_m r_o and takes 4 dB of it
• Output window: Ib/2·Rn + V_DSAT,2 < V_out < V_DD − Ib·Rp − V_DSAT,3. the output range in which both cascodes stay saturated; the 1 dB range the DC transfer reads lies inside it, about 0.51 to 0.80 V at tt
• Unity-gain frequency: f_u ≈ g_m1/(2π C_L). 42 MHz into 1 pF; the bandwidth is f_u over the gain, about 48 kHz
• Pole at the cascode's source: f_p2 ≈ g_m2/(2π C_x). at x, where M2's gate-source capacitance sits: a longer or wider M2 raises the gain but pulls this pole in towards f_u, and the phase margin with it

Trade-offs

• NMOS lengths (L1, Lc): longer raises R_out,n and the gain, until the PMOS side takes over; a longer cascode also brings the pole at x down towards f_u - a 3 µm cascode bought 1.2 dB for 12° of phase margin.
• Ladder resistors (Rp, Rn): larger drops give M4 and M1 more V_DS and more margin at the corners, but raise the window's floor and lower its ceiling.
• Stage current (N): more raises g_m1 and f_u but lowers every r_o in proportion, so the gain barely moves while the supply current grows.
• Output bias (VOB): the window hangs from V_DD, so the bias is set below V_DD; placed outside the window, one cascode leaves saturation and the gain collapses by tens of dB.

Testbenches and limits

• Operating point: The stage at its bias point, the servo holding its output where it is meant to sit: the current it draws and the input that takes.
• DC transfer: The transfer traced from one rail to the other by a servo of gain one: the output against the input, the gain against the output, and the output range - how far the output moves before that gain falls 1 dB from its peak.
• Gain and bandwidth: Gain and phase at the bias point, into the circuit's load.
• Output resistance: A 1 A AC current into the output with the input held at its bias: the voltage it makes is the output impedance.

Design variables and defaults

Ports

• in input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2016. Sec. 3.6 'Cascode Stage' (p. 82); the cascode bias from Ch. 5 'Current Mirrors and Biasing', Sec. 5.2 'Cascode Current Mirrors' (p. 139).

The topology - a common-source device under an NMOS cascode, loaded by a cascoded PMOS current source - and the result that each cascode multiplies the resistance below it by g_m r_o. The ladders, each a diode over a resistor so the device under a cascode keeps only the V_DS it needs, and the sizing are this library's, for SG13G2 at 1.2 V.