NMOS current mirror

How it works

Copies a reference current, a common building block of bias networks. M1 is diode-connected, so I_ref settles it at the V_GS that carries I_ref; M2 shares that gate voltage and, built as m copies of M1, approximately carries m·I_ref while saturated. In the nominal matched model, unequal drain voltages cause systematic copy error: M1's drain sits at V_GS1, M2's at V_out, and the output current slopes with the difference.

I_ref (10 µA by default) sets V_GS1 through the diode; M2 copies it as m·I_ref, with m the mirror ratio, and repeated unit geometry supports matching, but drain-voltage differences and random mismatch leave copy error.

Signal path

• Reference diode (M1): I_ref flows into its drain, tied to its gate, so it settles at the V_GS that carries exactly I_ref.
• Output copy (M2): Same gate voltage and m parallel copies of M1, so it approximately sinks m·I_ref from out while saturated; below the compliance voltage it enters triode.

Key relations

• Copy ratio: I_out/I_ref ≈ m (1 + λ V_out) / (1 + λ V_GS1). a first-order nominal model; equal drain voltages remove this systematic term, not random device mismatch
• Output resistance: R_out = r_o2 ≈ 1 / (λ I_out). the slope of the flat part of the curve; λ falls roughly as 1/L
• Compliance voltage: V_out,min ≈ V_GS1 − V_TH = V_ov. below it M2 leaves saturation and stops being a current source
• Diode voltage: V_GS1 ≈ V_TH + √(2 I_ref / (µ_n C_ox W/L)). square law; at the default 2 µm/2 µm and 10 µA the devices sit at the edge of strong inversion, V_ov ≈ 0.24 V

Trade-offs

• L: longer lowers λ, so copy error falls and R_out rises, at the cost of area and a larger V_ov, which raises the compliance voltage.
• W: wider lowers V_ov and with it the compliance voltage, at more area and capacitance.
• I_ref: more current raises V_ov and the compliance voltage, and lowers R_out, which falls as 1/I_out.
• Mirror ratio (unit devices): m unit copies approximately deliver m·I_ref without changing nominal unit geometry; R_out falls as 1/m.

Testbenches and limits

• Output characteristic

Design variables and defaults

Ports

• ref input: diode-connected, carries I_ref
• out output
• vdd supply
• 0 ground

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017. Current Mirrors - the simple MOS mirror, its copy accuracy and its output resistance.

The topology, and the result that the copy error is channel-length modulation rather than mismatch when the two devices are identical.