Differential pair with source degeneration

How it works

Separate tail sources keep the degeneration resistor out of the balanced common-mode current path. Differential current develops a voltage across RS that subtracts from the gate drive. When g_m R_S/2 is large, differential gain approaches 2R_D/R_S; finite transistor gain and headroom limit that approximation.

Ib, 10 µA, flows into the diode MB, and MT1 and MT2 each sink 20 µA from their side: 49 µA from the supply in all. With both inputs at 0.6 V the sources sit near 0.27 V, leaving each tail about 0.14 V above its V_DSAT, and both outputs sit 20 µA × 19.5 kΩ below V_DD, near 0.82 V. All three resistors are p+ poly: a material that moves little with temperature, and one they share, so the gain - a ratio of them, nearly - holds across the corners.

Signal path

• Tail sources (MB, MT1, MT2): Ib, fed into the ib pin, sets the diode MB; MT1 and MT2, N copies each, sink N·Ib from each side's source.
• Input pair (M1, M2): inp drives M1 and inn drives M2; their difference steers current through RS from one source to the other.
• Degeneration (RS): Between s1 and s2 it carries the steered current, so its drop takes up most of the input and each device's V_GS moves little - which is what keeps the pair linear.
• Loads (RD1, RD2): From vdd to outn, M1's drain, and to outp, M2's: outp rises as inp rises.

Key relations

• Differential gain: A_d = (v_outp − v_outn)/(v_inp − v_inn) ≈ g_m R_D/(1 + g_m R_S/2). g_m of one device: about 1.9 V/V at tt, where the same pair without RS gives 5
• Linear range: |v_id| ≲ N·Ib·R_S. the current RS can carry is at most one tail's; the gain holds within 1 dB over about ±0.26 V, against ±70 mV without RS
• Output common mode: V_out,CM = V_DD − N·Ib·R_D. it moves one for one with V_DD: the loads hang from it
• Headroom: V_DD − N·Ib·R_D − |v_od|/2 > V_CM + |v_id|/2 − V_TH. the output that falls must leave its device saturated: at a low supply this, more than RS, ends the range

Trade-offs

• Degeneration (RS): more widens the linear range and makes the gain a ratio of resistors, less sensitive to g_m's drift with temperature; the gain falls with it.
• Loads (RD): more gain, but the outputs sit lower and the falling one reaches its device's triode edge sooner; above 20 kΩ the resistors would be high-resistance poly, whose ratio to RS drifts by a third over temperature.
• Tail current (N): more g_m and a wider range, N·Ib·R_S, at more power and more drop across the loads.
• Split tail: two sources keep RS out of the common-mode path, so it costs no headroom - at the price of a second device, whose mismatch with the first flows through RS as offset.

Testbenches and limits

• Operating point: The pair with both inputs at their common mode: the current it draws and where its outputs sit.
• DC transfer: The differential input swept either side of balance at a fixed common mode: both outputs, the gain along the way, and how far the output swings before that gain falls 1 dB.
• Gain and bandwidth: Gain and phase at the bias point, into the circuit's load.

Design variables and defaults

Ports

• inp input (+)
• inn input (-)
• outp output
• outn output
• vdd supply
• vss ground
• ib bias: the reference current, fed into this pin

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2016. Sec. 4.2 'Basic Differential Pair' (p. 103), Secs. 4.2.1-4.2.2 qualitative and quantitative analysis (pp. 104, 106).

The resistively loaded NMOS pair and its large-signal analysis: the pair steers its tail current fully within a few overdrives. To that it adds the standard remedy, degeneration by a resistor between the sources, which trades gain for the range over which the pair is linear. The split tail and the sizing are this library's, for SG13G2 at 1.2 V.