Two-stage amplifier, two common-mode loops

How it works

A two-stage fully differential amplifier whose inputs each drive an NMOS and a PMOS device into one first-stage node, so the two transconductances add for one current. Common-source NMOS stages with Miller compensation follow. The two tails of the complementary stage leave its output level undefined, so a first common-mode loop sets the PMOS tail until a1 and a2 sit at a replica's gate voltage, and a second sets part of the output loads until the outputs sit where vocm asks.

The bench draws Ib out of the PMOS diode MB, whose gate the fixed PMOS sources share; MB1 feeds the NMOS diode MB2 for the tails, and MB3 feeds 2 Ib into MR, the replica of the second stage, whose gate voltage vr1 is the first loop's reference. Holding a1 and a2 at vr1 makes M5 and M6 run at N5 times MR's current by a count of devices. The output loop then sets M9, M10 until the loads match that current with the outputs at vocm, 0.6 V by default. The inputs sit at 0.42 V: a1 must stay above the NMOS pair's source and below the PMOS pair's, with room for both.

Signal path

• Complementary input (M1, M2, M3, M4, MTN, MTP, MTQ): inp drives M1 and M3, whose drains meet at a1; inn drives M2 and M4 at a2. MTN is the NMOS tail; the PMOS tail is MTP, fixed, and MTQ, set by the first-stage loop.
• Second stage (M5, M6, M7, M8, M9, M10): M5 and M6, N5 copies of the replica MR, amplify a1 and a2 onto outp and outn against fixed PMOS loads M7, M8 and the loads M9, M10 the output loop sets.
• Miller compensation (CC1, RZ1, CC2, RZ2): Each capacitor, with its nulling resistor, feeds back from an output to its first-stage node and splits the poles.
• First-stage loop (R1, R2, C1, C2, MC1, Q1, Q2, Q3, Q4, Q5): R1, R2 with C1, C2 average a1 and a2 onto cm1; Q1, Q2 compare it with vr1 on the 2:1 mirror Q3, Q4 and put the difference into the diode Q5, which MTQ copies: as a1 and a2 rise, the PMOS tail gives less.
• Output loop (R3, R4, C3, C4, MC2, Q6, Q7, Q8, Q9, Q10): R3, R4 with C3, C4 average the outputs onto cm2; Q6, Q7 compare it with vocm on the 2:1 mirror Q8, Q9 into the diode Q10, which M9, M10 copy: as the outputs rise, their loads give less.

Key relations

• Differential gain: A_d ≈ (g_m1 + g_m3)·(r_o1 ∥ r_o3 ∥ R1)·g_m5·(r_o5 ∥ r_o7 ∥ R3). The detector resistors load both stages, since each detector node is a differential ground.
• Unity-gain frequency: ω_u ≈ (g_m1 + g_m3)/C_c. C_c is CC1, 2 pF by default.
• Second-stage current: I_M5 = N5·I_MR. Because the first loop holds a1 at V_GS of MR, M5 is a mirror of it.
• Level window: V_icm − V_GS1 + V_DSAT1 < V_r1 < V_icm + V_SG3 − V_DSAT3. Where a1 may sit; it narrows when hot, so the pairs run in moderate inversion and MR near its zero-temperature-coefficient point.
• Output loop gain: T_2 ≈ 1.5·(g_m/I_D)·K·I_b·R_out. The share K·Ib of the load the loop controls, into the second stage's output resistance: about 30 dB, and the Miller capacitor holds that node near 1/g_m5 above the dominant pole.

Trade-offs

• Output loop share K: more gives the loop gain and accuracy, and more copies on Q10's node, which slows the loop's second pole.
• Input pair widths: wider lowers noise and V_GS, but narrows the window a1 must sit in when hot.
• Nulling resistor: sets where the zero lands against the output pole; too small costs margin at 125 °C, too large lowers the gain margin.
• Detector resistors: larger load the stages less, keeping gain, but slow each loop's sensing unless the capacitors across them bypass it.

Testbenches and limits

• Operating point: The amplifier as a unity-gain differential buffer, its inputs at their common mode: the current it draws, where its output common mode lands against the reference on vocm, and the differential offset.
• Open-loop gain: Differential gain and phase with the loop closed only at DC, through 1 TH inductors, so the operating point is the buffer's and every frequency sees the open loop.
• Common-mode loop gain: Each common-mode loop opened at the break point the circuit brings out, by Middlebrook's double injection - a voltage in series, then a current into the controlled side - with the differential loop closed as in the buffer: the loop's gain, its crossover, and its phase margin.
• Common-mode step: A 50mV step on the output common-mode reference, vocm, with the amplifier a unity-gain differential buffer: the output common mode follows it, and rings if its loop is short of margin.
• Step response: A 400mV differential step into the unity-gain differential buffer: how fast the differential output follows, whether it rings, and how far the output common mode is pushed on the way.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's differential output and its output common mode.
• Common-mode rejection: The same signal on both inputs, on the unity-gain buffer's input common mode: what reaches the differential output is the common-mode to differential gain over the differential one, and what reaches the output common mode is how firmly the common-mode loop holds it.
• Noise: Differential noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.

Design variables and defaults

Ports

• inp input
• inn input
• outp output
• outn output
• vdd supply
• vss ground
• vocm bias: the output common mode asked for
• ib bias: the reference current, drawn out of this pin
• cmo2 bias: the output common-mode amplifier's output, the diode Q10: the testbench joins it to cmg2, and breaks that loop there
• cmg2 bias: the gates of the loads M9, M10 the output loop sets
• cmo1 bias: the first-stage common-mode amplifier's output, the diode Q5: joined to cmg1 by the testbench
• cmg1 bias: the gate of MTQ, the part of the PMOS tail the first-stage loop sets

Reference

Y.-P. Hsu, Z. Liu, M. M. Hella, A -68 dB THD, 0.6 mm2 Active Area Biosignal Acquisition System With a 40-320 Hz Duty-Cycle Controlled Filter, 2020. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(1):48-59.

The topology of the filter's core amplifier: complementary input devices sharing each first-stage node, common-source NMOS second stages with Miller compensation, a common-mode loop holding the first stage through the PMOS tail and a second holding the outputs through the PMOS loads, each sensing through a resistive averager. The first loop's reference as the gate voltage of a replica of the second stage, the error amplifiers' current outputs into diodes, the split of tail and loads into fixed and controlled parts, the sizing and the targets are this library's, for SG13G2 at 1.2 V.