Flash ADC (3 bit)

How it works

Converts an input to three bits with one scheduled conversion per clock period by comparing it with every threshold at once. A string of eight equal resistors divides V_REF+ − V_REF− into taps one LSB apart, and seven comparators each report whether vin is above their tap; the result is a thermometer code whose count of ones is the output. Latches freeze that code on the falling clock edge, and a one-hot encoder turns it into three binary bits. The price is 2^N − 1 comparators for N bits. The displayed clock interval is calculated, not a measured output-valid delay.

The bench drives the comparator bias, 10 µA by default, into MB, and MT1..MT7 each copy it, so the comparators draw up to seven times the bias; V_REF+ and V_REF−, 0.9 and 0.3 V by default, set the range and pass (V_REF+ − V_REF−)/(8·R_L) down the ladder. The clock sets the timing: the latches follow while clk is high and hold while it is low.

Signal path

• Reference ladder (RL1..RL8): Eight equal poly resistors from V_REF+ down to V_REF− put tap k at V_REF− + k·LSB: seven thresholds, 75 mV apart by default.
• Comparators (MT1..MT7, MR1..MR7, MV1..MV7, ML1..ML7, MO1..MO7): Seven five-transistor amplifiers, vin on the gate of MVk and tap k on MRk; each pulls its output o_k low when vin is above its tap, all at once.
• Squaring (I1..I7): A NAND gate with both inputs on o_k, switching at 0.68 V where the amplifier balances, turns each output into t_k, 1 when vin is above tap k: a thermometer code.
• Latches (D1..D7): Transparent while clk is high, they close on its falling edge and hold full logic levels q_k while the encoder works through the low half.
• Encoder (H1..H6, E0, E1, E2): h_k = q_k and not q_(k+1) marks where the ones stop; each output bit ORs the one-hot lines whose code has it set, with q7 standing for code 7.

Key relations

• Tap voltages: V_k = V_rn + k·(V_rp − V_rn)/2^N. V_rp and V_rn are V_REF+ and V_REF−, on pins vrp and vrn; k = 1 to 7
• LSB: LSB = (V_rp − V_rn)/2^N. 75 mV with the defaults; ladder mismatch moves each tap by the unit errors below it
• Comparator count: n = 2^N − 1. seven here; each extra bit doubles them and halves the LSB each must resolve
• Systematic threshold offset: V_os ≈ (V_o,0 − V_M)/A_v; A_v = g_m·(r_on ∥ r_op). the amplifier must move o_k from balance to the squaring gate's threshold V_M; the NAND gate's V_M sits at V_o,0, 0.68 V, so V_os stays under 1.2 mV
• Comparator speed: dv_o/dt ≤ I_tail/C_o. the tail current slews each output node, which must settle before the latches close

Trade-offs

• Comparator bias: more current lets each comparator slew and settle faster, but seven tails copy it, so the supply current rises seven times as fast.
• Ladder unit: smaller units keep the taps stiff against the comparators' input kickback, but the references then supply more current, (V_REF+ − V_REF−)/(8·R_L).
• V_REF+ and V_REF−: a wider ladder enlarges the LSB, but the comparators convert right at every corner only for taps from about 0.33 to 0.88 V: higher, a hot fast corner moves the top threshold tens of millivolts; lower, the cold slow corner starves comparator 1.
• W (comparator input): a wider pair lowers random offset and raises g_m, but loads vin and every tap with more gate capacitance.

Testbenches and limits

• Transfer (input swept)
• Conversion (clocked): Eight conversions, every transistor simulated: about 8 s in the browser.

Design variables and defaults

Ports

• vin input
• vrp bias: the top of the ladder: the top of the input range
• vrn bias: the bottom of the ladder
• bn bias: the comparators' bias: the bench gives a current into MB
• clk clock: high: the latches follow the comparators; low: they hold
• b2 output
• b1 output
• b0 output
• vdd supply
• 0 ground

Reference

T. Chan Carusone, D. A. Johns and K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012. Nyquist-rate A/D converters - flash converters: the resistor string, the comparators, thermometer to 1-of-N to binary encoding, and bubble errors.

The architecture, the one-hot (ROM) encoder, and why a bubble in the thermometer code costs more than one code.

• B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995