Capacitively coupled chopper IA

How it works

An instrumentation amplifier for small, slow sensor signals whose gain is a capacitor ratio. The input chopper turns a DC input difference into a square wave that passes the input capacitors; the OTA amplifies it at the summing nodes, the chopper between its stages brings it back to baseband, and the feedback chopper returns the output onto the feedback capacitors, whose charge must cancel the input capacitors' at every edge. The OTA's own offset leaves at the chopping frequency instead - and a servo capacitor, chopped on its far side, keeps that moved offset from growing through the bias resistors.

The OTA is the single-loop chopper OTA, biased from Ib = 5 µA, its outputs held at vocm = 0.6 V by its common-mode loop. RB1, RB2 hold the summing nodes at vicm = 0.35 V, where the PMOS pair's tail keeps its headroom down to a 1.08 V supply, while the input capacitors separate the source's DC common mode from the OTA bias. The source is at 0.6 V in the benches and must still remain within the input switches' allowed voltage range. Every chopper runs from one complementary clock pair at 20 kHz: the default operating point is checked, but complementary clocks alone do not guarantee non-overlap at every signal voltage; clock timing needs verification before reuse.

Signal path

• Input chopper (SI1n, SI1p, SI2n, SI2p, SI3n, SI3p, SI4n, SI4p): Transmission gates join inp to xp and inn to xn while clk is high, and cross them while clkb is: a DC input difference becomes a square wave at the chopping frequency.
• Input capacitors (CI1, CI2): CI1, CI2 (10 pF) pass the chopped difference to the summing nodes sp, sn and block the source's common mode: at every edge each draws a charge C_in·v_id.
• Summing nodes (RB1, RB2, M1, M2): sp and sn are the OTA's pair gates, held at vicm = 0.35 V by RB1, RB2 (5 MΩ); the loop keeps them a virtual ground, so the resistors carry almost no signal.
• OTA (M3, M5, M7, M9, SO1, SO2, SO3, SO4, M11, M13, CC1, RZ1, MC1, MC4): The single-loop chopper OTA: its output chopper SO1-SO4, in step with the input chopper, brings the signal back to baseband at g1, g2 and sends the first stage's offset and 1/f noise up to the chopping frequency.
• Feedback chopper and capacitors (SF1n, SF1p, SF2n, SF2p, SF3n, SF3p, SF4n, SF4p, CF1, CF2): The outputs are chopped again and returned crosswise through CF1, CF2 (0.5 pF): at each edge each feedback capacitor transfers charge C_fb·v_od, opposing the input charge C_in·v_id, so charge balance gives v_od/v_id ≈ C_in/C_fb. The narrow gates slow this charge to match the input's.
• Servo (CS1, CS2, SS1, SS2, SS3, SS4): CS1, CS2 (2 pF) from the outputs, chopped on their far side onto the summing nodes. For the steady signal they carry nothing; for a ripple at the chopping frequency, and for the OTA's offset across the summing nodes, they carry a charge at every edge - a resistor 1/(4 f_ch C_s) from the chopped output to the summing nodes that the signal cannot see.

Key relations

• Gain: G = C_in/C_fb. 20 by the capacitors; 19.9 clocked at the defaults - the OTA's finite gain and the pair's gate capacitance take half a percent - and within about 1 % in every corner and draw.
• Input impedance: Z_in = 1/(2·f_ch·C_in). The input capacitors are recharged every half period: 2.5 MΩ at 20 kHz and 10 pF, as the clocked bench measures.
• The moved offset: D = (1 + R_sc/R_b)·V_os, R_sc = 1/(4·f_ch·C_s). The OTA's offset V_os leaves as a square wave of amplitude D at the output: R_sc = 6.25 MΩ against R_b = 5 MΩ holds it at 2.25·V_os - 9 mV peak to peak for the bench's 2 mV.
• Without the servo: dD/dt = V_os/(R_b·C_fb). The current the bias resistors draw from the offset would come off the feedback capacitors: 0.8 V/ms for 2 mV, to a rail within a millisecond.
• What chopping cannot move: V_os,res ≈ V_os,2/A_1. The second stage's own offset follows the output chopper: it is only divided by the first stage's gain, about 8 µV (one sigma) at the input with M11, M12 of 1.6 µm² units - the test offset itself leaves none.
• Bias-resistor noise: v_n,in ≈ √(4kT/R_b)/(2π·f_ch·C_in). About 45 nV/√Hz on each side at 5 MΩ, 20 kHz and 10 pF - the price of a resistor short enough to build.

Trade-offs

• Input capacitor (Cin): larger raises the gain for the same feedback capacitor and lowers the bias resistors' noise, but lowers the input impedance and takes area.
• Chopping frequency (fch): higher lowers the bias-resistor noise and the servo's resistance, but the input impedance falls with it, and every edge's spike comes more often.
• Servo capacitor (Cs): larger holds the moved offset closer to V_os and settles it in fewer edges, but loads the OTA's output; at 0 the ripple grows until the output hits a rail.
• Bias resistor (Rb): larger is quieter and shrinks the ripple, but costs about 0.31 mm of 0.5 µm poly per MΩ, and lets the pair's gate current move the summing nodes further from vicm.

Testbenches and limits

• Operating point, clocks held: The amplifier with its clocks held in one phase - every chopper straight - and no input: the current it draws and the levels it sits at. Held, the loop has no path at DC but the bias resistors, so this is the operating point the clocked benches start from, not a figure of the running amplifier.
• Clocked: gain and input impedance: The choppers clocked, a DC difference on the inputs. The gain is the output difference averaged over whole clock periods, against the capacitor ratio that should set it; the input impedance is the input difference over the current the source delivers, averaged the same way - the charge the input capacitors draw at every edge.
• Clocked: the moved offset: The choppers clocked, no input, and a test source (Vos, 2 mV by default) in series with the gate of M1 inside the amplifier: an OTA offset of known size. Chopped, it should leave baseband and come out as a ripple at the chopping frequency; the bench reads what is left of it at baseband, how large the ripple is, and whether it grows - an offset held on the feedback capacitors that leaks away through the bias resistors grows without end.

Design variables and defaults

Ports

• inp input
• inn input
• outp output
• outn output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin
• vocm bias: the output common mode
• vicm bias: the summing nodes' level, the input pair's common mode
• clk clock: high: every chopper straight
• clkb clock: high: every chopper crossed

Reference

Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa, A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes, 2011. IEEE Journal of Solid-State Circuits, 46(7):1534-1543.

The capacitively coupled chopper amplifier: input and feedback choppers around input and feedback capacitors, the OTA's output chopper between its stages. Ours: the common-mode loop around both stages, and the servo capacitor - a capacitor before a chopper rather than after it - which bounds the moved offset where the paper removes it with a ripple-reduction loop. The sizing is this library's, for SG13G2 at 1.2 V.