Inverter quantizer

How it works

A comparator made of one CMOS inverter. Its threshold is its own switching point V_M, where the pull-down M1 and the pull-up M2 carry the same current; near V_M both are saturated and the inverter has its full gain, so a sufficient input change drives the output towards a logic level. The nominal reference is established by relative transistor strengths, not an independent voltage reference. It moves with process, supply and temperature; mismatch moves individual devices' thresholds too.

There is no separate bias generator: the supply and the two widths set V_M, about 0.60 V at nominal from 1.2 V. Both devices conduct near the switching point. Farther from it, one device is mostly off, but leakage remains: the nominal operating-point bench records about 21 nA at an input 0.4 V from V_M.

Signal path

• Pull-down (M1): On once in rises past its threshold; it pulls out towards ground, harder the further in rises past V_M.
• Pull-up (M2): On while in is more than |V_TP| below V_DD; its width, 1.41 times M1's at one length, puts V_M in the middle of the supply.
• Decision (M1, M2): Near V_M both conduct and out moves steeply: an input a transition width past V_M gives a logic level, one closer leaves out in between.

Key relations

• Switching threshold: V_M = (V_TN + r (V_DD − |V_TP|))/(1 + r), r = √(β_p/β_n). square law; at 130 nm velocity saturation narrows the gap between the two devices, and W_p = 1.41 W_n centres V_M
• Gain at V_M: A_v = −(g_m1 + g_m2)(r_o1 ∥ r_o2). it sets how steep the transfer is at the threshold
• Transition width: ΔV_in(10–90 %) ≈ 0.8 V_DD/|A_v|. the output moves from 90% to 10% of supply over about 78 mV of input at nominal, a total band roughly centred on V_M; this is not a separately established logic noise-margin criterion
• Decision time: t_d ≈ C_L (V_DD/2)/I_D. I_D at the level the input steps to: 110 ps at 100 mV past V_M into 10 fF, 350 ps at 20 mV
• Supply sensitivity: dV_M/dV_DD ≈ r/(1 + r) ≈ 0.5. the threshold follows the supply at half its rate: this quantizer rejects nothing on V_DD

Trade-offs

• Width ratio (Wp over Wn): sets V_M; the skewed process corners still move it by ±3 % of V_DD whatever the ratio, since they strengthen one device against the other.
• Copies (M): more copies drive the load faster and average the mismatch - the threshold's spread from it falls as 1/√M - at more input capacitance for whatever drives the input.
• Length (L): longer channels add area and capacitance but barely steepen the transition, which the devices leaving saturation near the rails set as much as the gain at V_M does.

Testbenches and limits

• Decided states: The comparator with its input well past its thresholds, each way: the output levels and the current it draws in each state.
• Thresholds: V_in swept slowly across its thresholds, up and back down: where the output flips each way, the hysteresis between them, and the threshold at their midpoint.
• Decision time: The thresholds found first; then, for each overdrive from 20 mV to 300 mV, a step past each of them from 400 mV the other side, timed to the output at half the supply. 6 runs.

Design variables and defaults

Ports

• in input
• out output
• vdd supply
• vss ground

Reference

J. M. Rabaey, A. Chandrakasan, B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall, 2003. Ch. 5 'The CMOS Inverter': its voltage-transfer characteristic, switching threshold V_M and gain in the transition region.

The CMOS inverter and the result that its switching threshold is set by the pull-up to pull-down strength ratio, with the transition's steepness set by the gain there - which is what lets it serve as a one-bit quantizer against a threshold of its own. The sizing is this library's, for SG13G2 at 1.2 V.