Ibex RISC-V

How it works

A processor turns a stream of instructions into register updates and memory transactions. The instruction set describes what software observes; the pipeline describes how this implementation does the work.

• Fetch requests instruction bytes from external instruction memory. Compressed instructions are expanded before decoding.
• Decode reads operands and selects the ALU, multiply/divide unit or load/store operation. In the small preset, decode and execution share the second pipeline stage.
• Register results are written back; loads wait for a memory response. Branches and traps redirect instruction fetch, so not every cycle completes an instruction.
• A system wrapper must supply reset, boot configuration, instruction/data memory and interrupt/debug connections. The processor core alone is not a complete microcontroller.

Design decisions and limits

• Start with the small preset before adding caches, a third pipeline stage or security features. Each configuration needs its own verification evidence.
• The upstream core has an extensive verification flow. AiSIC's three directed programs check selected retirements and final state, not that full flow, all instructions or every configuration. No IHP qualification is claimed.
• Run changes the program test and memory latency without synthesis. The actual pinned RTL is precompiled to WebAssembly, not replaced by an instruction-set emulator. Editing RTL needs a new model build; a general browser SystemVerilog compiler is not provided.

Try it

Trace a load, an addition using its result, and a taken branch. Identify where memory latency stalls execution and which fetched instruction is discarded.

What runs in the browser

RTL simulation

Upstream sources

master snapshot · 8150e6455b91 · Apache-2.0 unless a file states otherwise; retain LICENSE, NOTICE and individual third-party notices when redistributing.

Pinned upstream tree