Core-supply LDO from 3.3 V

How it works

The 1.2 V core supply made from the 3.3 V I/O supply. The input is above what any 1.2 V device may see, so every transistor is a 3.3 V one; the output copies a 1.2 V reference through unity feedback to a five-transistor error amplifier. The thick-oxide devices give a great deal of gain - 88 dB of loop gain - and the design's hardest limit is on the other side: the output powers 1.2 V devices, rated 1.32 V, so the absolute transient peak must respect the load's voltage limit, including DC error.

Ib, 5 µA from outside, flows into the diode MB; the tail MT is 24 copies of it, 120 µA, which is what slews gate fast enough on a load release. The reference is an input, 1.2 V; the input is 3.3 V (2.97 to 3.63 V).

Signal path

• Error amplifier (M1, M2, M3, M4, MT): M1 senses the output, M2 the reference; the mirror M3, M4 turns M1's current onto gate, so a rise in the output lifts gate.
• Pass device (MP): A 3.3 V PMOS from the 3.3 V input: a higher gate means less current. With 2.1 V across it, it runs saturated and its own gain is large.
• Miller compensation (Rz, Cc): Cc across MP makes gate the dominant pole; Rz in series puts the zero in the left half-plane.
• Bleed (Rb): 200 µA through MP with no load: its g_m there places the output pole, and it narrows the swing of MP's V_SG between no load and full load.

Key relations

• Output voltage: V_out ≈ V_ref. Unity feedback.
• Zero resistor: 1/g_m,MP(no load) < Rz < 1/g_m2. Above the lower bound the zero is in the left half-plane; below the upper one the loop gain above the zero, about g_m2 · Rz, stays under 0 dB.
• Gate slew on load release: t_gate ≈ C_eff · ΔV_gate / I_charge. t_gate estimates gate-slew time. On load release the gate rises, V_SG falls and MP supplies less current. ΔV_gate is the required positive gate rise, C_eff its effective load and I_charge the available charging current; the delay contributes to output overshoot.
• Loop gain: T ≈ g_m2 · (r_o2 ∥ r_o4) · g_m,MP · R_o. Thick-oxide devices at 3.3 V have large r_o, and MP is saturated with 2.1 V across it.

Trade-offs

• Tail current (N): the release overshoot falls as it grows - 120 µA keeps it under 0.12 V at every corner - but it adds to the quiescent current alongside the 200 µA bleed.
• Wpass: a wider MP needs less V_SG swing between no load and full load, so less overshoot, at the cost of gate capacitance.
• Rb: a larger bleed narrows the V_SG swing and raises the output pole; it is quiescent current too.
• Cc: larger adds margin but slows the gate and raises the overshoot.

Testbenches and limits

• Operating point: The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.
• Load regulation: The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.
• Line regulation: The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.
• Dropout: The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.
• Loop gain: The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.
• Ringing across the loads: The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.
• Supply rejection: A ripple on the input, at the lightest and at the full load: how much of it reaches the output.
• Load step: The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.
• Line step: The input stepped across its rated range, 2.97 V to 3.63 V, and back, each edge 1.00 µs, at full load: how far the output moves.
• Output noise: The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.

Design variables and defaults

Ports

• ref input: the reference voltage, which the output copies
• sense input: the output as the regulator reads it
• out output
• vdd supply: the unregulated 3.3 V input
• vss ground
• ib bias: the bias current, driven into this pin

Reference

Z. Li, A. Chan Carusone, Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process, 2023. 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1-9.

The topology: a five-transistor error amplifier with the output fed straight back, a PMOS pass device, a Miller capacitor with a series resistor from its gate to the output, and a bleed. Here it makes the SG13G2 core supply from the 3.3 V I/O supply, so it is built on the 3.3 V devices; the sizing and specs are this library's.