Capless LDO, folded cascode and follower

How it works

An LDO that needs no large external output capacitor: 0.8 V from 1.2 V at up to 5 mA into 100 pF. A folded-cascode error amplifier gives the loop its gain; a PMOS source follower MF drives the wide pass device's gate from a low impedance, so the large gate is not the amplifier's load; and the compensation current is fed from the output into f2, the source of the cascode MC2, which passes it to the amplifier's output x. That splits the poles like a Miller capacitor without feeding the output forward - but it closes a second loop, which Cx on x keeps stable.

Ib, 5 µA, is drawn out of the ib pin through the PMOS diode MBP; MT (6 copies) is the tail, MBF (4) feeds the follower, MBQ (1) feeds the NMOS diode MBN through Rq, which sets the cascodes' gate vbc = V_GS,MBN + Ib · Rq. The sinks MN1, MN2 are 8 copies of MBN each. The reference is an input, 0.4 V.

Signal path

• Feedback divider and bleed (R1, R2, Rb): Two copies of one resistor: div is half the output, held at V_ref. Rb is the bleed that keeps the wide pass device's hot leakage from lifting the unloaded output.
• Folded-cascode amplifier (M1, M2, MN1, MN2, MC1, MC2, M3, M4): The PMOS pair M1 (div), M2 (ref) folds into the sinks MN1, MN2; the cascodes MC1, MC2 carry the rest up to the mirror M3, M4, whose output is x. A rise in div lifts x.
• Follower (MF, MBF): MF, with its well on its source, repeats x one V_SG higher on pg, the pass gate; MBF feeds it from the supply.
• Pass device (MP): A wide PMOS from the input to the output: a higher pg means less current.
• Compensation (Cc, Cx): Cc from the output into f2: its current reaches x through MC2, splitting the poles. Cx on x holds down the loop Cc closes through x, MF and MP.

Key relations

• Output voltage: V_out ≈ 2 · V_ref. Two equal units in the divider.
• Crossover: f_c ≈ (1/2) · g_m1/(2π · Cc). The compensation current enters at the cascode's low-impedance source.
• Inner loop: L_in ≈ (Cc/Cx) · g_m,MP · Z_out. At high frequency; without Cx it exceeds 0 dB up to about 25 MHz with no phase left, and the regulator oscillates at light load.
• Gate drive: V_SG,MP ≤ V_DD − (V_f2 + V_DSAT,MC2 + V_SG,MF). The follower costs one V_SG of drive: MP is wide, MF wide and long, to leave enough at a 1.08 V input.

Trade-offs

• Cx: too small and the inner loop rings or oscillates at light load; too large and the main loop's crossover and margin fall, and the load step dips further.
• Cc: sets the crossover; with Cx it sets the inner loop too, so the two scale together.
• Wf, Lf (MF): wider needs less V_SG and gives the pass device more drive; too short and it leaks, hot, enough to keep the pass gate below the supply at no load.
• Wpass: wider carries the load with less V_SG, but leaks more hot, which Rb must absorb.
• Lbn, Lm: long sinks and mirror lower the folded cascode's noise, at the price of saturation voltage the gate drive needs.

Testbenches and limits

• Operating point: The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.
• Load regulation: The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.
• Line regulation: The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.
• Dropout: The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.
• Loop gain: The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.
• Ringing across the loads: The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.
• Supply rejection: A ripple on the input, at the lightest and at the full load: how much of it reaches the output.
• Load step: The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.
• Line step: The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.
• Output noise: The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.

Design variables and defaults

Ports

• ref input: the reference voltage
• sense input: the output as the regulator reads it; the divider hangs from it
• out output
• vdd supply: the unregulated input
• vss ground
• ib bias: the bias current, drawn out of this pin

Reference

J. Li, H. Zhi, R. Lyu, W. Li, Z. Bi, K. Zhu, Y. Zeng, W. Shan, C. Yan, F. Yang, Y. Li, X. Zeng, AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis, 2024. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24), article 59, pp. 1-9.

The topology: a folded-cascode error amplifier with a PMOS input pair, a PMOS source follower driving the pass gate, and compensation from the output into the source of a cascode. Cx - the capacitor on the amplifier's output that keeps the second loop the compensation closes stable - the separate bleed, the sizing and the specs are this library's, for SG13G2 at 1.2 V.