LDO error amplifier, 3.3 V

How it works

The error amplifier of a low-dropout regulator that runs from a 3.3 V input rail: it compares the reference with the fed-back fraction of the output and drives the gate of the PMOS pass device, so its gain sets how closely the output holds its value and its offset sets how exactly. It is built from SG13G2's 3.3 V devices because it lives on that rail and must swing the pass gate across it. Two stages - an NMOS pair on a PMOS mirror, then a common-source PMOS - with a diode-connected PMOS between them that shifts the output device's gate a whole V_SG down, so a small output device runs at a large gate drive. The level shifter's current comes out of the first stage's output, and a twin of it drawn from the mirror's other side keeps the pair balanced. The 3.3 V devices match about half as well as the core ones, so the pair, mirror and twin need enough matching area.

The testbench feeds the 10 µA reference into the diode MB. MT, two copies, is the tail and MS, twenty copies, sinks the output stage's 200 µA; MLN and MLD keep MB's W/L on four times its area, so each carries its 10 µA - 252 µA in all. With MLD taking from d1 what MLS takes from d2, each mirror device carries 20 µA and each input device 10 µA. The pair (200 × 5 µm) runs near weak inversion, g_m/I_D 17.5; the mirror (72 × 5.5 µm) in stronger inversion, 5.7, at 0.99 V of V_SG.

Signal path

• Input pair (M1, M2, MT): MT's 20 µA divides between M1 and M2 by inp − inn. A rise on inp pulls d2 down through M2; the output stage inverts it back, so out follows inp.
• Mirror load (M3, M4, MLD): M3 turns the current on d1 - M1's and MLD's - into a gate voltage, and M4 copies it onto d2, where M2 and the level shifter draw theirs.
• Level shifter (MLS, MLN): Diode-connected MLS stands on d2, in its own n-well, and carries MLN's fixed 10 µA, so ls follows d2 1.03 V lower, with a gain close to one.
• Output stage (MO, MS): Common-source MO, its gate on ls, amplifies against the sink MS and inverts onto out; its 1.8 V of V_SG lets a 22 µm device carry 200 µA.
• Compensation (Cc, Rz): Cc in series with Rz, from d2 to out, is a Miller capacitor across the level shifter and the output stage; Rz moves its feed-forward zero into the left half-plane, just above the crossover.

Key relations

• DC gain: A_0 ≈ g_m2 (r_o2 ∥ r_o4) · g_mO (r_oO ∥ r_oS). The level shifter passes d2 to ls with a gain close to one, so it drops out. 3.3 V devices with long channels give about 94 dB.
• Unity-gain frequency: f_u ≈ g_m1/(2π C_c). About 0.17 mS into 15 pF: 1.9 MHz.
• Output pole: f_p2 ≈ g_mO/(2π C_L). C_L is the pass device's gate, 10 pF here. MO driven hard makes only 1.7 S/A, so the pole sits near 5.4 MHz: it takes 200 µA to keep it nearly three times above the crossover.
• Built-in offset, cancelled: V_os ≈ (I_MLN − I_MLD)/g_m1. Without MLD this is I_MLN/g_m1, 64 mV; with it only the two sinks' small difference is left, within 0.4 mV at every corner.
• Offset from mismatch: σ_os² = 2σ²_VT1 + 2(g_m3/g_m1)² σ²_VT3 + 2(I_LS (g_m/I_D)_LN/g_m1)² σ²_VTLN. With σ_VT = A_VT/√(W·L): the pair 0.31 mV, the mirror 0.21 mV - its mismatch scaled by g_m3/g_m1, 0.66 - and the twin 0.19 mV, 0.42 mV together. Forty draws show 0.46 mV σ.
• Output device's drive: V_SG,MO = (V_DD − v_d2) + V_SG,MLS. d2 rests about 0.77 V under V_DD, where MO carries MS's current, and MLS adds 1.03 V: 1.8 V of V_SG. As ls falls MO can source far more into the pass gate.

Trade-offs

• Area for offset: the pair gives most of it, so it is the largest device (1000 µm² each). At 40 × 2 µm the offset was 1.34 mV σ and a quarter of the draws missed ±2 mV; the price of 200 × 5 µm is input capacitance, which the real reference and feedback divider must drive.
• The mirror in stronger inversion reduces its input-referred mismatch through the factor g_m3/g_m1, but lowers the pair's drains and the top of the input range, and its larger gates put a pole near 7 MHz on d1: Cc grew from 12 to 15 pF and R_z to 6 kΩ to keep 80° of margin at the fast corner.
• A stronger level shift (narrower MLS, or its well on vdd) drives MO harder: a smaller MO and more pull-up, but less g_m per µA, a lower output pole, and a larger V_DSAT that lowers the top of the output range - by 0.17 V at the slow, hot corner with the well on vdd.
• More output current (N) raises g_mO and the output pole, allowing a smaller Cc and more bandwidth, and slews the pass gate faster downwards, at the cost of supply current - already 200 of the 252 µA.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
• Input common-mode range: Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.
• Output swing: The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, fed into this pin

Reference

Texas Instruments, TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO, Texas Instruments, 2022. Texas Instruments datasheet SBVS398A, Rev. A (original Dec. 2021).

The application: the error amplifier of a low-dropout regulator of that kind, run from the regulator's input and driving its PMOS pass device, with a level-shifted common-source output stage. The 3.3 V devices - chosen because the amplifier lives on a 3.3 V input rail and must swing the pass gate across it - the offset-cancelling twin of the level shifter, the sizing and the spec targets are this library's.