Folded-cascode LDO, 2.8 V from 3.3 V

How it works

A 2.8 V supply from the 3.3 V I/O supply, with only 0.17 V of headroom at the lowest input. The output copies a 2.8 V reference through unity feedback, so the error amplifier's input sits at 2.8 V: too close to the supply for a five-transistor amplifier's input pair, which needs room under its load. The folded input pair connects to current sources near the supply, leaving more drain headroom at this input level. Every transistor is a 3.3 V one.

Ib, 5 µA from outside, into MB; the tail MT is 8 copies of it, the sinks M9 and M10 4 each. The reference is an input, 2.8 V; the input is 3.3 V (2.97 to 3.63 V).

Signal path

• Input pair (M1, M2, MT): M1 senses the output, M2 the reference, both near 2.8 V; their drains fold into f1 and f2, just under the supply.
• Folded cascode (M5, M6, M7, M8, M9, M10): M5, M6 on top are a mirror gated from mir, the drain of the cascode M7; M8 carries the output side down to gate against the sink M10. A rise in the output lifts gate.
• Cascode bias (MB2, MBC): MBC, a narrow PMOS diode fed by a copy of Ib, sets vbc so that M5, M6 keep about 0.25 V and M7, M8 stay saturated.
• Pass device and compensation (MP, Rz, Cc, Rb): A 3.3 V PMOS from the input; Cc with Rz across it splits the poles, and Rb is the bleed.

Key relations

• Input range: V_CM,max ≈ V_DD − V_DSAT,M5 + V_GS1 − V_DSAT1. Above the supply for this design: the input-stage estimate reaches above the intended common mode, but terminal-voltage ratings still apply.
• Output swing at no load: V_DD − V_gate ≥ V_DSAT,M6 + V_DSAT,M8. With no load gate sits only about 0.6 V below the supply; M6 and M8 run in weak inversion so both fit.
• Loop gain: T ≈ g_m2 · R_gate · g_m,MP · R_o. R_gate: the cascoded output resistance; at the lowest input MP runs in triode and T falls to about 31 dB.
• Noise: v_n,in² ≈ v_n,M1² · (1 + g_m,M5/g_m1 + g_m,M9/g_m1). The folded branches' current sources add their noise: extra current-source noise must be budgeted; the comparison with another amplifier depends on sizing and current allocation.

Trade-offs

• Wc, Lc (MBC): too wide and vbc sits too high, leaving M5, M6 in triode; too narrow and M7, M8 run out of room.
• K against N: more sink current speeds the output and the line step, but its noise and the mirror's grow against the pair's transconductance.
• Wp, Wk: wider M5-M8 run in weak inversion with small saturation voltages, which the 0.6 V at no load needs; wider still adds capacitance and noise.
• Rb: the bleed sets MP's g_m at no load, and so the output pole.

Testbenches and limits

• Operating point: The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.
• Load regulation: The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.
• Line regulation: The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.
• Dropout: The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.
• Loop gain: The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.
• Ringing across the loads: The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.
• Supply rejection: A ripple on the input, at the lightest and at the full load: how much of it reaches the output.
• Load step: The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.
• Line step: The input stepped across its rated range, 2.97 V to 3.63 V, and back, each edge 1.00 µs, at full load: how far the output moves.
• Output noise: The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.

Design variables and defaults

Ports

• ref input: the reference voltage, which the output copies
• sense input: the output as the regulator reads it
• out output
• vdd supply: the unregulated 3.3 V input
• vss ground
• ib bias: the bias current, driven into this pin

Reference

Z. Li, A. Chan Carusone, Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process, 2023. 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1-9.

The topology: a folded-cascode error amplifier with an NMOS input pair and PMOS cascodes, unity feedback, a PMOS pass device compensated by a Miller capacitor with a series resistor, and a bleed. Its bias is referenced to one current, the cascodes' gate made inside; the sizing, the 2.8 V output and the specs are this library's, on SG13G2's 3.3 V devices.