PMOS LDO, Miller and feed-forward compensated

How it works

A PMOS-pass LDO compensated from inside for a 100 pF load, with no zero resistor. Cc straight from the pass device's gate to its drain splits the poles, and leaves a right-half-plane zero at g_m,MP/Cc that takes phase near the crossover at light load. Cf across the divider's upper resistor gives phase back from the feedback side: above 1/(2π R1 Cf) the divider passes more of the output to div, a zero-pole pair that leads the phase. The rest is the basic LDO's core: 0.9 V from 1.2 V at up to 5 mA.

Ib, 10 µA from outside, flows into the diode MB; the tail MT is N copies of it, 40 µA. The reference is an input, 0.6 V, and the supply is 1.2 V (1.08 to 1.32 V).

Signal path

• Feedback divider (R1, R2, R3): Three copies of one resistor, one above div and two below: div is two thirds of the output, and the loop holds it at V_ref. Their 30 µA are also the least MP ever carries.
• Feed-forward capacitor (Cf, R1): Cf bypasses R1: the feedback factor rises from 2/3 towards 1 between its zero and its pole, and the loop gains up to 11.5° of phase there.
• Error amplifier (M1, M2, M3, M4, MT): M1 takes div and M2 the reference, on the tail MT; the mirror M3, M4 turns M1's current round onto gate, so a rise in div lifts gate.
• Pass device (MP): A common-source PMOS from the input to the output: a higher gate means less current, so the output falls back.
• Miller compensation (Cc, MP): Cc across MP makes gate the dominant pole and sets the crossover; with nothing in series it also feeds gate forward to the output, a right-half-plane zero.

Key relations

• Feedback factor: β(s) = (2/3) · (1 + s · R1 · Cf)/(1 + s · (R1 ∥ 2R1) · Cf). A zero at 1/(2π · R1 · Cf) and a pole 1.5 times higher: the most lead such a pair gives is asin(1/5) = 11.5°.
• Crossover: f_c ≈ β · g_m2/(2π · Cc). Slightly higher where Cf has lifted β.
• Right-half-plane zero: f_z = g_m,MP/(2π · Cc). Lowest at no load, where it costs the most phase: the margin is least there.

Trade-offs

• Cf: placed so its pair sits at the no-load crossover it adds its full lead; much larger and the pair slides below the crossover and gives nothing back.
• Cc: larger lowers the crossover and the right-half-plane zero together - their ratio is approximately g_m,MP/(β g_m2) - so it buys margin mainly through the output pole.
• Compared with a zero resistor, Cf cannot move the zero at all; it can only lead the phase a little, which gives about 64° versus 93° worst-load phase margin for the two default designs at the nominal condition.

Testbenches and limits

• Operating point: The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.
• Load regulation: The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.
• Line regulation: The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.
• Dropout: The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.
• Loop gain: The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.
• Ringing across the loads: The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.
• Supply rejection: A ripple on the input, at the lightest and at the full load: how much of it reaches the output.
• Load step: The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.
• Line step: The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.
• Output noise: The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.

Design variables and defaults

Ports

• ref input: the reference voltage
• sense input: the output as the regulator reads it; the divider hangs from it
• out output
• vdd supply: the unregulated input
• vss ground
• ib bias: the bias current, driven into this pin

Reference

G. A. Rincon-Mora, Analog IC Design with Low-Dropout Regulators, 2nd, McGraw-Hill, 2014. the PMOS-pass LDO, its feedback divider and its frequency compensation.

The topology: a five-transistor error amplifier, a PMOS pass device, a Miller capacitor across it and a feed-forward capacitor across the divider's upper resistor. The sizing and specs are this library's, for SG13G2 at 1.2 V.

• B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2016