LDO reference amplifier, self-biased

How it works

The amplifier that, in a low-dropout regulator, carries the reference voltage from the bandgap to the error amplifier as a unity-gain buffer - so its offset and noise contribute to output error through the regulator's reference-to-output gain. It is a two-stage Miller op amp: an NMOS pair on a PMOS mirror, then a common-source PMOS, the two gains multiplying, with Cc and its nulling resistor splitting the poles. It has no bias pin: a PMOS and an NMOS diode in series across the supply set its current. That current moves with V_DD and the corners, but every current in the amplifier is a copy of it, so the stages stay balanced and the phase margin holds.

MP, long and strongly inverted, takes 0.85 V of the supply and MN 0.35 V, which sets 3.8 µA at 27 °C - 2.2 µA slow, hot and 10 % low, 6.9 µA fast, cold and 10 % high. MT, two copies of MN, feeds the pair about 4 µA a side; M6, four copies, sinks 17 µA, and M5, four copies of the mirror unit, sources it at the mirror's current density, so d2 rests at d1's voltage. 28 µA in all.

Signal path

• Self-bias (MP, MN): Two diodes in series across the supply: their gate-source voltages add up to V_DD, which fixes the current through both, and MN's gate voltage nx carries it to the copies.
• Input pair (M1, M2, MT): MT, two copies of MN, feeds the pair; a rise on inp steers current into M2 and pulls d2 down.
• Mirror load (M3, M4): M3 turns M1's current into a gate voltage on d1 and M4 copies it onto d2, where both halves of the signal current meet.
• Second stage (M5, M6): Common-source M5, gate on d2, amplifies against M6, S copies of MN, and inverts onto out, so out follows inp.
• Compensation (Cc, Rz): Cc from d2 to out, multiplied by the second stage's gain, makes d2 the dominant pole; Rz, just above 1/g_m5, keeps the zero Cc makes in the left half-plane.

Key relations

• Reference current: V_SG,MP(I_ref) + V_GS,MN(I_ref) = V_DD. Two diodes across the supply fix I_ref, so it rises with V_DD and moves with both thresholds: about 3:1 over the corners.
• DC gain: A_0 ≈ g_m2 (r_o2 ∥ r_o4) · g_m5 (r_o5 ∥ r_o6). In both stages the NMOS r_o is the shorter: about 65 dB.
• Unity-gain frequency: f_u ≈ g_m1/(2π C_c). 94 µS into 3 pF, about 4.6 MHz; it follows the self-set current, from 2.0 to 12 MHz over the corners.
• Compensation zero: f_z = 1/[2π C_c (R_z − 1/g_m5)]. R_z is 6 kΩ against 1/g_m5 of 3 kΩ at 27 °C and about 5 kΩ where the current is lowest: the zero stays in the left half-plane, above the crossover.
• Highest input: V_CM,max = V_DD − V_SG3 − V_DSAT1 + V_GS1. The weakly inverted mirror's small V_SG keeps the 0.76 V reference inside the range even with the supply 10 % low: 0.87 V there.
• Reduced systematic offset: (W/L)_5/(W/L)_3 = I_M6/I_M3 = S. Repeated units set nominal current density; finite output resistance and mismatch leave residual offset.

Trade-offs

• A wider MP raises the reference current and every current with it: more bandwidth and less noise, at a supply current that already spans 3:1 over the corners.
• A larger mirror unit (Wp, Lp) lowers its flicker noise - 219 nV/√Hz at 20 × 1 µm, 167 nV/√Hz at 30 × 1.5 µm - but M5, S copies of it, loads d2 with its gate and pulls the output pole in: at 40 × 2 µm the margin fell to 62° at the fast corner.
• A mirror in stronger inversion lowers its noise contribution further but raises V_SG3, and with it the top of the input range falls below the 0.76 V reference at the low supply.
• Cc: larger lowers the bandwidth and the slew rate and adds phase margin; the current it is charged with moves 3:1 with the corners, so settling does too.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 100mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
• Input common-mode range: Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.
• Output swing: The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground

Reference

Texas Instruments, TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO, Texas Instruments, 2022. Texas Instruments datasheet SBVS398A, Rev. A (original Dec. 2021).

The application: the reference amplifier of a low-dropout regulator of that kind, which carries the reference voltage to the error amplifier, so its offset, noise and supply rejection reach the regulated output. The circuit - a self-biased two-stage Miller op amp - its sizing for the library's 0.76 V bandgap and 1.2 V supply, and its spec targets are this library's.