Unity-feedback PMOS LDO

How it works

A PMOS-pass LDO with no divider: the output goes straight back to M1 in the five-transistor error amplifier, so the loop holds it at the reference, 0.6 V from a 1.2 V input at up to 5 mA. The whole loop gain regulates and no divider multiplies the amplifier's noise. The price is that the amplifier's input sits at the output: its tail node rides one V_GS below it, which caps how high the output can be and how far down the amplifier can pull the pass device's gate.

Ib, 10 µA from outside, flows into the diode MB; the tail MT is two copies of it, 20 µA. The reference is an input, 0.6 V, and the supply is 1.2 V (1.08 to 1.32 V).

Signal path

• Reference input (Rr): The reference reaches M2 through Rr, the resistance of whatever drives it; M2 draws little DC gate current, so a moderate Rr produces little DC drop; Rr and input capacitance also limit bandwidth.
• Error amplifier (M1, M2, M3, M4, MT): M1 senses the output itself, M2 the reference; the mirror M3, M4 turns M1's current onto gate, so a rise in the output lifts gate.
• Pass device (MP): Common-source PMOS: a higher gate means less current and the output falls back to the reference.
• Compensation and output (Cc, Co, Rb): Cc from the output back to gate splits the poles; Co is the capacitor the regulator carries on its own output, and Rb the bleed that keeps MP conducting - and sets its g_m - with no load.

Key relations

• Output voltage: V_out ≈ V_ref. Unity feedback; the offset of M1, M2 is the output's error one for one.
• Common mode: V_ref − V_GS1 < V_DD − V_SG3 − V_DSAT1. M1 must stay saturated between its tail and its diode-connected load: at 1.08 V this caps the output near 0.6 V.
• Right-half-plane zero: f_z / f_c = g_m,MP/g_m2. Cc sets both, so only a larger bleed or a smaller tail moves the zero away from the crossover.
• Dropout: V_DO = V_in,min − V_out,98. Measured at full load when the output is 2% below its nominal-input level. The amplifier cannot pull the gate below about 0.45 V, contributing to the measured 0.31 V dropout.

Trade-offs

• Vref: a higher output squeezes M1 between its tail and its load and raises the dropout; at 0.7 V the slow, hot corner runs out of headroom.
• W1 (M1, M2): a wider pair has less V_GS, which lifts the tail node and squeezes M1 further - the opposite of what it does elsewhere.
• Rb: less bleed current saves power but lowers g_m,MP at no load, bringing the output pole and the right-half-plane zero towards the crossover.
• Rr: its thermal noise reaches the output one for one; a few tens of kΩ at most.

Testbenches and limits

• Operating point: The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.
• Load regulation: The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.
• Line regulation: The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.
• Dropout: The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.
• Loop gain: The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.
• Ringing across the loads: The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.
• Supply rejection: A ripple on the input, at the lightest and at the full load: how much of it reaches the output.
• Load step: The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.
• Line step: The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.
• Output noise: The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.

Design variables and defaults

Ports

• ref input: the reference voltage, which the output copies
• sense input: the output as the regulator reads it
• out output
• vdd supply: the unregulated input
• vss ground
• ib bias: the bias current, driven into this pin

Reference

G. A. Rincon-Mora, Analog IC Design with Low-Dropout Regulators, 2nd, McGraw-Hill, 2014. the PMOS-pass LDO, its error amplifier and its frequency compensation.

The topology: a five-transistor error amplifier fed back from the output directly, a PMOS pass device, a Miller capacitor from the output to the pass gate, and a bleed and a capacitor on the output. The sizing and specs are this library's, for SG13G2 at 1.2 V.