4-bit synchronous counter

How it works

All four state bits share one clock. Combinational logic computes the next count, and muxes hold the old state when EN is low.

• Compute bit toggles from the lower bits.
• Use enable muxes before four resettable flip-flops.
• Verify hold, increment, wraparound and asynchronous reset.

Design decisions and limits

• The carry chain affects the register-to-register path, so frequency needs timing analysis rather than a truth-table check.
• The shown cell areas exclude placement whitespace, clock tree, routing, taps, power delivery and pads.

Try it

Find a held count and the 15-to-0 wraparound. Why is this a synchronous counter rather than a ripple counter?

Interface

What runs in the browser

Logic check · Cell transistors · Gate delays · SPICE · mapped cells · 22 expected-output checks · 14 IHP cells in the explicit example